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Merge tag 'irqchip-6.2' of git://git.kernel.org/pub/scm/linux/kernel/…
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…git/maz/arm-platforms into irq/core

Pull irqchip updates frim Marc Zyngier:

 - More APCI fixes and improvements for the LoongArch architecture,
   adding support for the HTVEC irqchip, suspend-resume, and some
   PCI INTx workarounds

 - Initial DT support for LoongArch. I'm not even kidding.

 - Support for the MTK CIRQv2, a minor deviation from the original version

 - Error handling fixes for wpcm450, GIC...

 - BE detection for a FSL controller

 - Declare the Sifive PLIC as wake-up agnostic

 - Simplify fishing out the device data for the ST irqchip

 - Mark some data structures as __initconst in the apple-aic driver

 - Switch over from strtobool to kstrtobool

 - COMPILE_TEST fixes
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Thomas Gleixner committed Dec 7, 2022
2 parents e6d2210 + 6ed54e1 commit 6132a49
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Original file line number Diff line number Diff line change
@@ -0,0 +1,34 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LoongArch CPU Interrupt Controller

maintainers:
- Liu Peibao <liupeibao@loongson.cn>

properties:
compatible:
const: loongarch,cpu-interrupt-controller

'#interrupt-cells':
const: 1

interrupt-controller: true

additionalProperties: false

required:
- compatible
- '#interrupt-cells'
- interrupt-controller

examples:
- |
interrupt-controller {
compatible = "loongarch,cpu-interrupt-controller";
#interrupt-cells = <1>;
interrupt-controller;
};

This file was deleted.

Original file line number Diff line number Diff line change
@@ -0,0 +1,68 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mtk-cirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek System Interrupt Controller

maintainers:
- Youlin Pei <youlin.pei@mediatek.com>

description:
In MediaTek SoCs, the CIRQ is a low power interrupt controller designed to
work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.
The external interrupts (outside MCUSYS) will feed through CIRQ and connect
to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
interrupts and generate a pulse signal to parent interrupt controller when
flush command is executed. With CIRQ, MCUSYS can be completely turned off
to improve the system power consumption without losing interrupts.


properties:
compatible:
items:
- enum:
- mediatek,mt2701-cirq
- mediatek,mt8135-cirq
- mediatek,mt8173-cirq
- mediatek,mt8192-cirq
- const: mediatek,mtk-cirq

reg:
maxItems: 1

'#interrupt-cells':
const: 3

interrupt-controller: true

mediatek,ext-irq-range:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: First CIRQ interrupt
- description: Last CIRQ interrupt
description:
Identifies the range of external interrupts in different SoCs

required:
- compatible
- reg
- '#interrupt-cells'
- interrupt-controller
- mediatek,ext-irq-range

additionalProperties: false

examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
cirq: interrupt-controller@10204000 {
compatible = "mediatek,mt2701-cirq", "mediatek,mtk-cirq";
reg = <0x10204000 0x400>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&sysirq>;
mediatek,ext-irq-range = <32 200>;
};
2 changes: 1 addition & 1 deletion arch/loongarch/include/asm/irq.h
Original file line number Diff line number Diff line change
Expand Up @@ -93,7 +93,7 @@ int liointc_acpi_init(struct irq_domain *parent,
int eiointc_acpi_init(struct irq_domain *parent,
struct acpi_madt_eio_pic *acpi_eiointc);

struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
int htvec_acpi_init(struct irq_domain *parent,
struct acpi_madt_ht_pic *acpi_htvec);
int pch_lpc_acpi_init(struct irq_domain *parent,
struct acpi_madt_lpc_pic *acpi_pchlpc);
Expand Down
6 changes: 4 additions & 2 deletions drivers/acpi/pci_irq.c
Original file line number Diff line number Diff line change
Expand Up @@ -387,13 +387,15 @@ int acpi_pci_irq_enable(struct pci_dev *dev)
u8 pin;
int triggering = ACPI_LEVEL_SENSITIVE;
/*
* On ARM systems with the GIC interrupt model, level interrupts
* On ARM systems with the GIC interrupt model, or LoongArch
* systems with the LPIC interrupt model, level interrupts
* are always polarity high by specification; PCI legacy
* IRQs lines are inverted before reaching the interrupt
* controller and must therefore be considered active high
* as default.
*/
int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ?
int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ||
acpi_irq_model == ACPI_IRQ_MODEL_LPIC ?
ACPI_ACTIVE_HIGH : ACPI_ACTIVE_LOW;
char *link = NULL;
char link_desc[16];
Expand Down
3 changes: 2 additions & 1 deletion drivers/irqchip/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ config ALPINE_MSI

config AL_FIC
bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
depends on OF || COMPILE_TEST
depends on OF
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
help
Expand Down Expand Up @@ -576,6 +576,7 @@ config IRQ_LOONGARCH_CPU
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
select LOONGSON_HTVEC
select LOONGSON_LIOINTC
select LOONGSON_EIOINTC
select LOONGSON_PCH_PIC
Expand Down
6 changes: 3 additions & 3 deletions drivers/irqchip/irq-apple-aic.c
Original file line number Diff line number Diff line change
Expand Up @@ -248,14 +248,14 @@ struct aic_info {
bool fast_ipi;
};

static const struct aic_info aic1_info = {
static const struct aic_info aic1_info __initconst = {
.version = 1,

.event = AIC_EVENT,
.target_cpu = AIC_TARGET_CPU,
};

static const struct aic_info aic1_fipi_info = {
static const struct aic_info aic1_fipi_info __initconst = {
.version = 1,

.event = AIC_EVENT,
Expand All @@ -264,7 +264,7 @@ static const struct aic_info aic1_fipi_info = {
.fast_ipi = true,
};

static const struct aic_info aic2_info = {
static const struct aic_info aic2_info __initconst = {
.version = 2,

.irq_cfg = AIC2_IRQ_CFG,
Expand Down
2 changes: 1 addition & 1 deletion drivers/irqchip/irq-gic-pm.c
Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,7 @@ static int gic_probe(struct platform_device *pdev)

pm_runtime_enable(dev);

ret = pm_runtime_get_sync(dev);
ret = pm_runtime_resume_and_get(dev);
if (ret < 0)
goto rpm_disable;

Expand Down
3 changes: 2 additions & 1 deletion drivers/irqchip/irq-gic-v3.c
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/kstrtox.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
Expand Down Expand Up @@ -1171,7 +1172,7 @@ static bool gicv3_nolpi;

static int __init gicv3_nolpi_cfg(char *buf)
{
return strtobool(buf, &gicv3_nolpi);
return kstrtobool(buf, &gicv3_nolpi);
}
early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);

Expand Down
3 changes: 2 additions & 1 deletion drivers/irqchip/irq-gic.c
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/kstrtox.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/list.h>
Expand Down Expand Up @@ -1332,7 +1333,7 @@ static bool gicv2_force_probe;

static int __init gicv2_force_probe_cfg(char *buf)
{
return strtobool(buf, &gicv2_force_probe);
return kstrtobool(buf, &gicv2_force_probe);
}
early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);

Expand Down
48 changes: 36 additions & 12 deletions drivers/irqchip/irq-loongarch-cpu.c
Original file line number Diff line number Diff line change
Expand Up @@ -92,18 +92,34 @@ static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = {
.xlate = irq_domain_xlate_onecell,
};

static int __init
liointc_parse_madt(union acpi_subtable_headers *header,
const unsigned long end)
#ifdef CONFIG_OF
static int __init cpuintc_of_init(struct device_node *of_node,
struct device_node *parent)
{
cpuintc_handle = of_node_to_fwnode(of_node);

irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM,
&loongarch_cpu_intc_irq_domain_ops, NULL);
if (!irq_domain)
panic("Failed to add irqdomain for loongarch CPU");

set_handle_irq(&handle_cpu_irq);

return 0;
}
IRQCHIP_DECLARE(cpu_intc, "loongson,cpu-interrupt-controller", cpuintc_of_init);
#endif

static int __init liointc_parse_madt(union acpi_subtable_headers *header,
const unsigned long end)
{
struct acpi_madt_lio_pic *liointc_entry = (struct acpi_madt_lio_pic *)header;

return liointc_acpi_init(irq_domain, liointc_entry);
}

static int __init
eiointc_parse_madt(union acpi_subtable_headers *header,
const unsigned long end)
static int __init eiointc_parse_madt(union acpi_subtable_headers *header,
const unsigned long end)
{
struct acpi_madt_eio_pic *eiointc_entry = (struct acpi_madt_eio_pic *)header;

Expand All @@ -112,16 +128,24 @@ eiointc_parse_madt(union acpi_subtable_headers *header,

static int __init acpi_cascade_irqdomain_init(void)
{
acpi_table_parse_madt(ACPI_MADT_TYPE_LIO_PIC,
liointc_parse_madt, 0);
acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC,
eiointc_parse_madt, 0);
int r;

r = acpi_table_parse_madt(ACPI_MADT_TYPE_LIO_PIC, liointc_parse_madt, 0);
if (r < 0)
return r;

r = acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC, eiointc_parse_madt, 0);
if (r < 0)
return r;

return 0;
}

static int __init cpuintc_acpi_init(union acpi_subtable_headers *header,
const unsigned long end)
{
int ret;

if (irq_domain)
return 0;

Expand All @@ -139,9 +163,9 @@ static int __init cpuintc_acpi_init(union acpi_subtable_headers *header,
set_handle_irq(&handle_cpu_irq);
acpi_set_irq_model(ACPI_IRQ_MODEL_LPIC, lpic_get_gsi_domain_id);
acpi_set_gsi_to_irq_fallback(lpic_gsi_to_irq);
acpi_cascade_irqdomain_init();
ret = acpi_cascade_irqdomain_init();

return 0;
return ret;
}

IRQCHIP_ACPI_DECLARE(cpuintc_v1, ACPI_MADT_TYPE_CORE_PIC,
Expand Down
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