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Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
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Synopsys DesignWare AXI DMA Controller | ||
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Required properties: | ||
- compatible: "snps,axi-dma-1.01a" | ||
- reg: Address range of the DMAC registers. This should include | ||
all of the per-channel registers. | ||
- interrupt: Should contain the DMAC interrupt number. | ||
- interrupt-parent: Should be the phandle for the interrupt controller | ||
that services interrupts for this device. | ||
- dma-channels: Number of channels supported by hardware. | ||
- snps,dma-masters: Number of AXI masters supported by the hardware. | ||
- snps,data-width: Maximum AXI data width supported by hardware. | ||
(0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits) | ||
- snps,priority: Priority of channel. Array size is equal to the number of | ||
dma-channels. Priority value must be programmed within [0:dma-channels-1] | ||
range. (0 - minimum priority) | ||
- snps,block-size: Maximum block size supported by the controller channel. | ||
Array size is equal to the number of dma-channels. | ||
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Optional properties: | ||
- snps,axi-max-burst-len: Restrict master AXI burst length by value specified | ||
in this property. If this property is missing the maximum AXI burst length | ||
supported by DMAC is used. [1:256] | ||
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Example: | ||
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dmac: dma-controller@80000 { | ||
compatible = "snps,axi-dma-1.01a"; | ||
reg = <0x80000 0x400>; | ||
clocks = <&core_clk>, <&cfgr_clk>; | ||
clock-names = "core-clk", "cfgr-clk"; | ||
interrupt-parent = <&intc>; | ||
interrupts = <27>; | ||
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dma-channels = <4>; | ||
snps,dma-masters = <2>; | ||
snps,data-width = <3>; | ||
snps,block-size = <4096 4096 4096 4096>; | ||
snps,priority = <0 1 2 3>; | ||
snps,axi-max-burst-len = <16>; | ||
}; |
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obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac-platform.o |
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