CHROMIUM: pinctrl: tegra210: xusb: Fix improper HS_CURR_LEVEL

Add HS_CURR_LEVEL range checking to avoid a USB2 failure.
This is to make sure the value to be programmed for HS_CURR_LEVEL,
the sum of fuse.hs_curr_level (e.g. 3) and hs_curr_level_offset
(e.g. -4, specified in .dtsi file), is in valid range from 0 to 0x3F.

BUG=None
TEST=Set fuse.hs_curr_level to 3, value to be programmed (3-4= -1,
use 0) is 0 and in valid range.
Set fuse.hs_curr_level to 0x46, value to be programmed (0x46-4= 0x42,
use 0x3f) is 0x3f and in valid range.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/320980
Reviewed-by: Mark Kuo <mkuo@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 634e917)
Signed-off-by: David Riley <davidriley@chromium.org>
Change-Id: I591fd1c0ed9a782ecf3c1d9a0db558ff54827ed9
Reviewed-on: https://chrome-internal-review.googlesource.com/245447
Reviewed-by: David Riley <davidriley@google.com>
Commit-Queue: David Riley <davidriley@google.com>
Tested-by: David Riley <davidriley@google.com>

drivers/pinctrl/pinctrl-tegra210-xusb.c

@@ -1148,9 +1148,9 @@ static int tegra210_utmi_phy_power_on(struct phy *phy)
 		   XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD |
 		   XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 |
 		   XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
-	value |= (priv->fuse.hs_curr_level[port] +
-		  utmi->hs_curr_level_offset) <<
-		 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT;
+	value |= (((u32) clamp_val((s32) priv->fuse.hs_curr_level[port] +
+		   utmi->hs_curr_level_offset, 0, 0x3f)) <<
+		  XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT);
 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(port));
 
 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(port));