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ASoC: da7219: Update PLL ranges and dividers to improve locking
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The expected MCLK frequency ranges and the associated dividers
are updated to improve PLL locking in a corner scenario, with low
MCLK frequency near an input divider change boundary.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Adam Thomson authored and Mark Brown committed Apr 19, 2016
1 parent f55532a commit 63a450a
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Showing 2 changed files with 24 additions and 24 deletions.
28 changes: 14 additions & 14 deletions sound/soc/codecs/da7219.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1079,21 +1079,21 @@ static int da7219_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
dev_err(codec->dev, "PLL input clock %d below valid range\n",
da7219->mclk_rate);
return -EINVAL;
} else if (da7219->mclk_rate <= 5000000) {
indiv_bits = DA7219_PLL_INDIV_2_5_MHZ;
indiv = DA7219_PLL_INDIV_2_5_MHZ_VAL;
} else if (da7219->mclk_rate <= 10000000) {
indiv_bits = DA7219_PLL_INDIV_5_10_MHZ;
indiv = DA7219_PLL_INDIV_5_10_MHZ_VAL;
} else if (da7219->mclk_rate <= 20000000) {
indiv_bits = DA7219_PLL_INDIV_10_20_MHZ;
indiv = DA7219_PLL_INDIV_10_20_MHZ_VAL;
} else if (da7219->mclk_rate <= 40000000) {
indiv_bits = DA7219_PLL_INDIV_20_40_MHZ;
indiv = DA7219_PLL_INDIV_20_40_MHZ_VAL;
} else if (da7219->mclk_rate <= 4500000) {
indiv_bits = DA7219_PLL_INDIV_2_TO_4_5_MHZ;
indiv = DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL;
} else if (da7219->mclk_rate <= 9000000) {
indiv_bits = DA7219_PLL_INDIV_4_5_TO_9_MHZ;
indiv = DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL;
} else if (da7219->mclk_rate <= 18000000) {
indiv_bits = DA7219_PLL_INDIV_9_TO_18_MHZ;
indiv = DA7219_PLL_INDIV_9_TO_18_MHZ_VAL;
} else if (da7219->mclk_rate <= 36000000) {
indiv_bits = DA7219_PLL_INDIV_18_TO_36_MHZ;
indiv = DA7219_PLL_INDIV_18_TO_36_MHZ_VAL;
} else if (da7219->mclk_rate <= 54000000) {
indiv_bits = DA7219_PLL_INDIV_40_54_MHZ;
indiv = DA7219_PLL_INDIV_40_54_MHZ_VAL;
indiv_bits = DA7219_PLL_INDIV_36_TO_54_MHZ;
indiv = DA7219_PLL_INDIV_36_TO_54_MHZ_VAL;
} else {
dev_err(codec->dev, "PLL input clock %d above valid range\n",
da7219->mclk_rate);
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20 changes: 10 additions & 10 deletions sound/soc/codecs/da7219.h
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Original file line number Diff line number Diff line change
Expand Up @@ -194,11 +194,11 @@
/* DA7219_PLL_CTRL = 0x20 */
#define DA7219_PLL_INDIV_SHIFT 2
#define DA7219_PLL_INDIV_MASK (0x7 << 2)
#define DA7219_PLL_INDIV_2_5_MHZ (0x0 << 2)
#define DA7219_PLL_INDIV_5_10_MHZ (0x1 << 2)
#define DA7219_PLL_INDIV_10_20_MHZ (0x2 << 2)
#define DA7219_PLL_INDIV_20_40_MHZ (0x3 << 2)
#define DA7219_PLL_INDIV_40_54_MHZ (0x4 << 2)
#define DA7219_PLL_INDIV_2_TO_4_5_MHZ (0x0 << 2)
#define DA7219_PLL_INDIV_4_5_TO_9_MHZ (0x1 << 2)
#define DA7219_PLL_INDIV_9_TO_18_MHZ (0x2 << 2)
#define DA7219_PLL_INDIV_18_TO_36_MHZ (0x3 << 2)
#define DA7219_PLL_INDIV_36_TO_54_MHZ (0x4 << 2)
#define DA7219_PLL_MCLK_SQR_EN_SHIFT 5
#define DA7219_PLL_MCLK_SQR_EN_MASK (0x1 << 5)
#define DA7219_PLL_MODE_SHIFT 6
Expand Down Expand Up @@ -761,11 +761,11 @@
#define DA7219_PLL_FREQ_OUT_98304 98304000

/* PLL Frequency Dividers */
#define DA7219_PLL_INDIV_2_5_MHZ_VAL 1
#define DA7219_PLL_INDIV_5_10_MHZ_VAL 2
#define DA7219_PLL_INDIV_10_20_MHZ_VAL 4
#define DA7219_PLL_INDIV_20_40_MHZ_VAL 8
#define DA7219_PLL_INDIV_40_54_MHZ_VAL 16
#define DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL 1
#define DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL 2
#define DA7219_PLL_INDIV_9_TO_18_MHZ_VAL 4
#define DA7219_PLL_INDIV_18_TO_36_MHZ_VAL 8
#define DA7219_PLL_INDIV_36_TO_54_MHZ_VAL 16

/* SRM */
#define DA7219_SRM_CHECK_RETRIES 8
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