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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kerne…
…l/git/clk/linux Pull clk updates from Stephen Boyd: "This time we have a good set of changes to the core framework that do some general cleanups, but nothing too major. The majority of the diff goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is introduced for Actions Semi so it takes up some lines to add all the different types, and the Qualcomm diff is there because we add support for two SoCs and it's quite a bit of data. Otherwise the big driver updates are on TI Davinci and Amlogic platforms. And then the long tail of driver updates for various fixes and stuff follows after that. Core: - debugfs cleanups removing error checking and an unused provider API - Removal of a clk init typedef that isn't used - Usage of match_string() to simplify parent string name matching - OF clk helpers moved to their own file (linux/of_clk.h) - Make clk warnings more readable across kernel versions New Drivers: - Qualcomm SDM845 GCC and Video clk controllers - Qualcomm MSM8998 GCC - Actions Semi S900 SoC support - Nuvoton npcm750 microcontroller clks - Amlogic axg AO clock controller Removed Drivers: - Deprecated Rockchip clk-gate driver Updates: - debugfs functions stopped checking return values - Support for the MSIOF module clocks on Rensas R-Car M3-N - Support for the new Rensas RZ/G1C and R-Car E3 SoCs - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs - Berlin and Amlogic SPDX tagging - Usage of of_clk_get_parent_count() in more places - Proper implementation of the CDEV1/2 clocks on Tegra20 - Allwinner H6 PRCM clock support and R40 EMAC support - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet - Round closest support for meson's mpll driver - Support for meson8b nand clocks and gxbb video decoder clocks - Mediatek mali clks - STM32MP1 fixes - Uniphier LD11/LD20 stream demux system clock" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) clk: qcom: Export clk_fabia_pll_configure() clk: bcm: Update and add Stingray clock entries dt-bindings: clk: Update Stingray binding doc clk-si544: Properly round requested frequency to nearest match clk: ingenic: jz4770: Add 150us delay after enabling VPU clock clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle clk: ingenic: jz4770: Change OTG from custom to standard gated clock clk: ingenic: Support specifying "wait for clock stable" delay clk: ingenic: Add support for clocks whose gate bit is inverted clk: use match_string() helper clk: bcm2835: use match_string() helper clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions clk: imx6: add EPIT clock support clk: mvebu: use correct bit for 98DX3236 NAND ...
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Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
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MediaTek g3dsys controller | ||
============================ | ||
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The MediaTek g3dsys controller provides various clocks and reset controller to | ||
the GPU. | ||
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Required Properties: | ||
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- compatible: Should be: | ||
- "mediatek,mt2701-g3dsys", "syscon": | ||
for MT2701 SoC | ||
- "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon": | ||
for MT7623 SoC | ||
- #clock-cells: Must be 1 | ||
- #reset-cells: Must be 1 | ||
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The g3dsys controller uses the common clk binding from | ||
Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
The available clocks are defined in dt-bindings/clock/mt*-clk.h. | ||
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Example: | ||
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g3dsys: clock-controller@13000000 { | ||
compatible = "mediatek,mt7623-g3dsys", | ||
"mediatek,mt2701-g3dsys", | ||
"syscon"; | ||
reg = <0 0x13000000 0 0x200>; | ||
#clock-cells = <1>; | ||
#reset-cells = <1>; | ||
}; |
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Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
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* Actions S900 Clock Management Unit (CMU) | ||
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The Actions S900 clock management unit generates and supplies clock to various | ||
controllers within the SoC. The clock binding described here is applicable to | ||
S900 SoC. | ||
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Required Properties: | ||
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- compatible: should be "actions,s900-cmu" | ||
- reg: physical base address of the controller and length of memory mapped | ||
region. | ||
- clocks: Reference to the parent clocks ("hosc", "losc") | ||
- #clock-cells: should be 1. | ||
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Each clock is assigned an identifier, and client nodes can use this identifier | ||
to specify the clock which they consume. | ||
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All available clocks are defined as preprocessor macros in | ||
dt-bindings/clock/actions,s900-cmu.h header and can be used in device | ||
tree sources. | ||
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External clocks: | ||
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The hosc clock used as input for the plls is generated outside the SoC. It is | ||
expected that it is defined using standard clock bindings as "hosc". | ||
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Actions S900 CMU also requires one more clock: | ||
- "losc" - internal low frequency oscillator | ||
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Example: Clock Management Unit node: | ||
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cmu: clock-controller@e0160000 { | ||
compatible = "actions,s900-cmu"; | ||
reg = <0x0 0xe0160000 0x0 0x1000>; | ||
clocks = <&hosc>, <&losc>; | ||
#clock-cells = <1>; | ||
}; | ||
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Example: UART controller node that consumes clock generated by the clock | ||
management unit: | ||
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uart: serial@e012a000 { | ||
compatible = "actions,s900-uart", "actions,owl-uart"; | ||
reg = <0x0 0xe012a000 0x0 0x2000>; | ||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&cmu CLK_UART5>; | ||
}; |
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Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt
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* Nuvoton NPCM7XX Clock Controller | ||
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Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which | ||
generates and supplies clocks to all modules within the BMC. | ||
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External clocks: | ||
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There are six fixed clocks that are generated outside the BMC. All clocks are of | ||
a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and | ||
clk_sysbypck are inputs to the clock controller. | ||
clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the | ||
network. They are set on the device tree, but not used by the clock module. The | ||
network devices use them directly. | ||
Example can be found below. | ||
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All available clocks are defined as preprocessor macros in: | ||
dt-bindings/clock/nuvoton,npcm7xx-clock.h | ||
and can be reused as DT sources. | ||
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Required Properties of clock controller: | ||
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- compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton | ||
Poleg BMC NPCM750 | ||
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- reg: physical base address of the clock controller and length of | ||
memory mapped region. | ||
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- #clock-cells: should be 1. | ||
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Example: Clock controller node: | ||
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clk: clock-controller@f0801000 { | ||
compatible = "nuvoton,npcm750-clk"; | ||
#clock-cells = <1>; | ||
reg = <0xf0801000 0x1000>; | ||
clock-names = "refclk", "sysbypck", "mcbypck"; | ||
clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; | ||
}; | ||
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Example: Required external clocks for network: | ||
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/* external reference clock */ | ||
clk_refclk: clk-refclk { | ||
compatible = "fixed-clock"; | ||
#clock-cells = <0>; | ||
clock-frequency = <25000000>; | ||
clock-output-names = "refclk"; | ||
}; | ||
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/* external reference clock for cpu. float in normal operation */ | ||
clk_sysbypck: clk-sysbypck { | ||
compatible = "fixed-clock"; | ||
#clock-cells = <0>; | ||
clock-frequency = <800000000>; | ||
clock-output-names = "sysbypck"; | ||
}; | ||
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/* external reference clock for MC. float in normal operation */ | ||
clk_mcbypck: clk-mcbypck { | ||
compatible = "fixed-clock"; | ||
#clock-cells = <0>; | ||
clock-frequency = <800000000>; | ||
clock-output-names = "mcbypck"; | ||
}; | ||
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/* external clock signal rg1refck, supplied by the phy */ | ||
clk_rg1refck: clk-rg1refck { | ||
compatible = "fixed-clock"; | ||
#clock-cells = <0>; | ||
clock-frequency = <125000000>; | ||
clock-output-names = "clk_rg1refck"; | ||
}; | ||
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/* external clock signal rg2refck, supplied by the phy */ | ||
clk_rg2refck: clk-rg2refck { | ||
compatible = "fixed-clock"; | ||
#clock-cells = <0>; | ||
clock-frequency = <125000000>; | ||
clock-output-names = "clk_rg2refck"; | ||
}; | ||
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clk_xin: clk-xin { | ||
compatible = "fixed-clock"; | ||
#clock-cells = <0>; | ||
clock-frequency = <50000000>; | ||
clock-output-names = "clk_xin"; | ||
}; | ||
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Example: GMAC controller node that consumes two clocks: a generated clk by the | ||
clock controller and a fixed clock from DT (clk_rg1refck). | ||
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ethernet0: ethernet@f0802000 { | ||
compatible = "snps,dwmac"; | ||
reg = <0xf0802000 0x2000>; | ||
interrupts = <0 14 4>; | ||
interrupt-names = "macirq"; | ||
clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; | ||
clock-names = "stmmaceth", "clk_gmac"; | ||
}; |
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Qualcomm Technologies, Inc. RPMh Clocks | ||
------------------------------------------------------- | ||
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Resource Power Manager Hardened (RPMh) manages shared resources on | ||
some Qualcomm Technologies Inc. SoCs. It accepts clock requests from | ||
other hardware subsystems via RSC to control clocks. | ||
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Required properties : | ||
- compatible : shall contain "qcom,sdm845-rpmh-clk" | ||
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- #clock-cells : must contain 1 | ||
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Example : | ||
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#include <dt-bindings/clock/qcom,rpmh.h> | ||
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&apps_rsc { | ||
rpmhcc: clock-controller { | ||
compatible = "qcom,sdm845-rpmh-clk"; | ||
#clock-cells = <1>; | ||
}; | ||
}; |
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Qualcomm Video Clock & Reset Controller Binding | ||
----------------------------------------------- | ||
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Required properties : | ||
- compatible : shall contain "qcom,sdm845-videocc" | ||
- reg : shall contain base register location and length | ||
- #clock-cells : from common clock binding, shall contain 1. | ||
- #power-domain-cells : from generic power domain binding, shall contain 1. | ||
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Optional properties : | ||
- #reset-cells : from common reset binding, shall contain 1. | ||
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Example: | ||
videocc: clock-controller@ab00000 { | ||
compatible = "qcom,sdm845-videocc"; | ||
reg = <0xab00000 0x10000>; | ||
#clock-cells = <1>; | ||
#power-domain-cells = <1>; | ||
}; |
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