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Merge branch 'patchwork' into v4l_for_linus
* patchwork: (496 commits) [media] v4l: tvp5150: Add missing break in set control handler [media] v4l: tvp5150: Don't inline the tvp5150_selmux() function [media] v4l: tvp5150: Compile tvp5150_link_setup out if !CONFIG_MEDIA_CONTROLLER [media] em28xx: don't store usb_device at struct em28xx [media] em28xx: use usb_interface for dev_foo() calls [media] em28xx: don't change the device's name [media] mn88472: fix chip id check on probe [media] mn88473: fix chip id check on probe [media] lirc: fix error paths in lirc_cdev_add() [media] s5p-mfc: Add support for MFC v8 available in Exynos 5433 SoCs [media] s5p-mfc: Rework clock handling [media] s5p-mfc: Don't keep clock prepared all the time [media] s5p-mfc: Kill all IS_ERR_OR_NULL in clocks management code [media] s5p-mfc: Remove dead conditional code [media] s5p-mfc: Ensure that clock is disabled before turning power off [media] s5p-mfc: Remove special clock rate management [media] s5p-mfc: Use printk_ratelimited for reporting ioctl errors [media] s5p-mfc: Set DMA_ATTR_ALLOC_SINGLE_PAGES [media] vivid: Set color_enc on HSV formats [media] v4l2-tpg: Init hv_enc field with a valid value ...
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109 changes: 109 additions & 0 deletions
109
Documentation/devicetree/bindings/media/mediatek-mdp.txt
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* Mediatek Media Data Path | ||
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Media Data Path is used for scaling and color space conversion. | ||
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Required properties (controller (parent) node): | ||
- compatible: "mediatek,mt8173-mdp" | ||
- mediatek,vpu: the node of video processor unit, see | ||
Documentation/devicetree/bindings/media/mediatek-vpu.txt for details. | ||
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Required properties (all function blocks, child node): | ||
- compatible: Should be one of | ||
"mediatek,mt8173-mdp-rdma" - read DMA | ||
"mediatek,mt8173-mdp-rsz" - resizer | ||
"mediatek,mt8173-mdp-wdma" - write DMA | ||
"mediatek,mt8173-mdp-wrot" - write DMA with rotation | ||
- reg: Physical base address and length of the function block register space | ||
- clocks: device clocks, see | ||
Documentation/devicetree/bindings/clock/clock-bindings.txt for details. | ||
- power-domains: a phandle to the power domain, see | ||
Documentation/devicetree/bindings/power/power_domain.txt for details. | ||
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Required properties (DMA function blocks, child node): | ||
- compatible: Should be one of | ||
"mediatek,mt8173-mdp-rdma" | ||
"mediatek,mt8173-mdp-wdma" | ||
"mediatek,mt8173-mdp-wrot" | ||
- iommus: should point to the respective IOMMU block with master port as | ||
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt | ||
for details. | ||
- mediatek,larb: must contain the local arbiters in the current Socs, see | ||
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt | ||
for details. | ||
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Example: | ||
mdp { | ||
compatible = "mediatek,mt8173-mdp"; | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
ranges; | ||
mediatek,vpu = <&vpu>; | ||
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mdp_rdma0: rdma@14001000 { | ||
compatible = "mediatek,mt8173-mdp-rdma"; | ||
reg = <0 0x14001000 0 0x1000>; | ||
clocks = <&mmsys CLK_MM_MDP_RDMA0>, | ||
<&mmsys CLK_MM_MUTEX_32K>; | ||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; | ||
iommus = <&iommu M4U_PORT_MDP_RDMA0>; | ||
mediatek,larb = <&larb0>; | ||
}; | ||
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mdp_rdma1: rdma@14002000 { | ||
compatible = "mediatek,mt8173-mdp-rdma"; | ||
reg = <0 0x14002000 0 0x1000>; | ||
clocks = <&mmsys CLK_MM_MDP_RDMA1>, | ||
<&mmsys CLK_MM_MUTEX_32K>; | ||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; | ||
iommus = <&iommu M4U_PORT_MDP_RDMA1>; | ||
mediatek,larb = <&larb4>; | ||
}; | ||
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mdp_rsz0: rsz@14003000 { | ||
compatible = "mediatek,mt8173-mdp-rsz"; | ||
reg = <0 0x14003000 0 0x1000>; | ||
clocks = <&mmsys CLK_MM_MDP_RSZ0>; | ||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; | ||
}; | ||
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mdp_rsz1: rsz@14004000 { | ||
compatible = "mediatek,mt8173-mdp-rsz"; | ||
reg = <0 0x14004000 0 0x1000>; | ||
clocks = <&mmsys CLK_MM_MDP_RSZ1>; | ||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; | ||
}; | ||
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mdp_rsz2: rsz@14005000 { | ||
compatible = "mediatek,mt8173-mdp-rsz"; | ||
reg = <0 0x14005000 0 0x1000>; | ||
clocks = <&mmsys CLK_MM_MDP_RSZ2>; | ||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; | ||
}; | ||
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mdp_wdma0: wdma@14006000 { | ||
compatible = "mediatek,mt8173-mdp-wdma"; | ||
reg = <0 0x14006000 0 0x1000>; | ||
clocks = <&mmsys CLK_MM_MDP_WDMA>; | ||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; | ||
iommus = <&iommu M4U_PORT_MDP_WDMA>; | ||
mediatek,larb = <&larb0>; | ||
}; | ||
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mdp_wrot0: wrot@14007000 { | ||
compatible = "mediatek,mt8173-mdp-wrot"; | ||
reg = <0 0x14007000 0 0x1000>; | ||
clocks = <&mmsys CLK_MM_MDP_WROT0>; | ||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; | ||
iommus = <&iommu M4U_PORT_MDP_WROT0>; | ||
mediatek,larb = <&larb0>; | ||
}; | ||
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mdp_wrot1: wrot@14008000 { | ||
compatible = "mediatek,mt8173-mdp-wrot"; | ||
reg = <0 0x14008000 0 0x1000>; | ||
clocks = <&mmsys CLK_MM_MDP_WROT1>; | ||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; | ||
iommus = <&iommu M4U_PORT_MDP_WROT1>; | ||
mediatek,larb = <&larb4>; | ||
}; | ||
}; |
57 changes: 53 additions & 4 deletions
57
Documentation/devicetree/bindings/media/mediatek-vcodec.txt
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Renesas R-Car Fine Display Processor (FDP1) | ||
------------------------------------------- | ||
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The FDP1 is a de-interlacing module which converts interlaced video to | ||
progressive video. It is capable of performing pixel format conversion between | ||
YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are supported as | ||
an input to the module. | ||
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Required properties: | ||
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- compatible: must be "renesas,fdp1" | ||
- reg: the register base and size for the device registers | ||
- interrupts : interrupt specifier for the FDP1 instance | ||
- clocks: reference to the functional clock | ||
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Optional properties: | ||
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- power-domains: reference to the power domain that the FDP1 belongs to, if | ||
any. | ||
- renesas,fcp: a phandle referencing the FCP that handles memory accesses | ||
for the FDP1. Not needed on Gen2, mandatory on Gen3. | ||
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Please refer to the binding documentation for the clock and/or power domain | ||
providers for more details. | ||
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Device node example | ||
------------------- | ||
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fdp1@fe940000 { | ||
compatible = "renesas,fdp1"; | ||
reg = <0 0xfe940000 0 0x2400>; | ||
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&cpg CPG_MOD 119>; | ||
power-domains = <&sysc R8A7795_PD_A3VP>; | ||
renesas,fcp = <&fcpf0>; | ||
}; |
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