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Merge branch 'net-phy-mediatek-add-token-ring-helper-functions'
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Sky Huang says:

====================
net: phy: mediatek: Add token-ring helper functions

This patchset add token-ring helper functions and moves some macros from
mtk-ge.c into mtk-phy-lib.c.

v2: https://lore.kernel.org/20250116012159.3816135-2-SkyLake.Huang@mediatek.com
====================

Link: https://patch.msgid.link/20250213080553.921434-1-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Jakub Kicinski committed Feb 18, 2025
2 parents 1dd1bf5 + be378eb commit 6626f11
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Showing 4 changed files with 341 additions and 125 deletions.
296 changes: 192 additions & 104 deletions drivers/net/phy/mediatek/mtk-ge-soc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,107 @@
#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)

#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5

/* Registers on Token Ring debug nodes */
/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
/* NormMseLoThresh */
#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8)

/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
/* RemAckCntLimitCtrl */
#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1)

/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */
/* VcoSlicerThreshBitsHigh */
#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */
/* DfeTailEnableVgaThresh1000 */
#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */
/* MrvlTrFix100Kp */
#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20)
/* MrvlTrFix100Kf */
#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17)
/* MrvlTrFix1000Kp */
#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14)
/* MrvlTrFix1000Kf */
#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */
/* VgaDecRate */
#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
/* SlvDSPreadyTime */
#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
/* MasDSPreadyTime */
#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
/* EnabRandUpdTrig */
#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8)

/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
/* ResetSyncOffset */
#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */
/* FfeUpdGainForceVal */
#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7)
/* FfeUpdGainForce */
#define FFE_UPDATE_GAIN_FORCE BIT(6)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
/* TrFreeze */
#define TR_FREEZE_MASK GENMASK(11, 0)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
/* SS: Steady-state, KP: Proportional Gain */
/* SSTrKp100 */
#define SS_TR_KP100_MASK GENMASK(21, 19)
/* SSTrKf100 */
#define SS_TR_KF100_MASK GENMASK(18, 16)
/* SSTrKp1000Mas */
#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13)
/* SSTrKf1000Mas */
#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10)
/* SSTrKp1000Slv */
#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7)
/* SSTrKf1000Slv */
#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
/* clear this bit if wanna select from AFE */
/* Regsigdet_sel_1000 */
#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
/* RegEEE_st2TrKf1000 */
#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */
/* RegEEE_slv_waketr_timer_tar */
#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11)
/* RegEEE_slv_remtx_timer_tar */
#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */
/* RegEEE_slv_wake_int_timer_tar */
#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */
/* RegEEE_trfreeze_timer2 */
#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
/* RegEEE100Stg1_tar */
#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)

/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
/* REGEEE_wake_slv_tr_wait_dfesigdet_en */
#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11)

#define ANALOG_INTERNAL_OPERATION_MAX_US 20
#define TXRESERVE_MIN 0
Expand Down Expand Up @@ -701,40 +801,36 @@ static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
static void mt798x_phy_common_finetune(struct phy_device *phydev)
{
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
__phy_write(phydev, 0x11, 0xc71);
__phy_write(phydev, 0x12, 0xc);
__phy_write(phydev, 0x10, 0x8fae);

/* EnabRandUpdTrig = 1 */
__phy_write(phydev, 0x11, 0x2f00);
__phy_write(phydev, 0x12, 0xe);
__phy_write(phydev, 0x10, 0x8fb0);

/* NormMseLoThresh = 85 */
__phy_write(phydev, 0x11, 0x55a0);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x83aa);

/* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
__phy_write(phydev, 0x11, 0x240);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x9680);

/* TrFreeze = 0 (mt7988 default) */
__phy_write(phydev, 0x11, 0x0);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x9686);

/* SSTrKp100 = 5 */
/* SSTrKf100 = 6 */
/* SSTrKp1000Mas = 5 */
/* SSTrKf1000Mas = 6 */
/* SSTrKp1000Slv = 5 */
/* SSTrKf1000Slv = 6 */
__phy_write(phydev, 0x11, 0xbaef);
__phy_write(phydev, 0x12, 0x2e);
__phy_write(phydev, 0x10, 0x968c);
__mtk_tr_modify(phydev, 0x1, 0xf, 0x17,
SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK,
FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));

__mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18,
ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER);

__mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
NORMAL_MSE_LO_THRESH_MASK,
FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55));

__mtk_tr_modify(phydev, 0x2, 0xd, 0x0,
FFE_UPDATE_GAIN_FORCE_VAL_MASK,
FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
FFE_UPDATE_GAIN_FORCE);

__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK);

__mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
SS_TR_KP100_MASK | SS_TR_KF100_MASK |
SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK |
SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK,
FIELD_PREP(SS_TR_KP100_MASK, 0x5) |
FIELD_PREP(SS_TR_KF100_MASK, 0x6) |
FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) |
FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) |
FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) |
FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6));

phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
}

Expand All @@ -757,27 +853,29 @@ static void mt7981_phy_finetune(struct phy_device *phydev)
}

phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
/* ResetSyncOffset = 6 */
__phy_write(phydev, 0x11, 0x600);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x8fc0);
__mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
RESET_SYNC_OFFSET_MASK,
FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6));

/* VgaDecRate = 1 */
__phy_write(phydev, 0x11, 0x4c2a);
__phy_write(phydev, 0x12, 0x3e);
__phy_write(phydev, 0x10, 0x8fa4);
__mtk_tr_modify(phydev, 0x1, 0xf, 0x12,
VGA_DECIMATION_RATE_MASK,
FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1));

/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
* MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
*/
__phy_write(phydev, 0x11, 0xd10a);
__phy_write(phydev, 0x12, 0x34);
__phy_write(phydev, 0x10, 0x8f82);
__mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) |
FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) |
FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) |
FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2));

/* VcoSlicerThreshBitsHigh */
__phy_write(phydev, 0x11, 0x5555);
__phy_write(phydev, 0x12, 0x55);
__phy_write(phydev, 0x10, 0x8ec0);
__mtk_tr_modify(phydev, 0x1, 0xd, 0x20,
VCO_SLICER_THRESH_HIGH_MASK,
FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555));
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);

/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
Expand Down Expand Up @@ -829,25 +927,23 @@ static void mt7988_phy_finetune(struct phy_device *phydev)
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);

phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
/* ResetSyncOffset = 5 */
__phy_write(phydev, 0x11, 0x500);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x8fc0);
__mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
RESET_SYNC_OFFSET_MASK,
FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5));

/* VgaDecRate is 1 at default on mt7988 */

/* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
* MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
*/
__phy_write(phydev, 0x11, 0xb90a);
__phy_write(phydev, 0x12, 0x6f);
__phy_write(phydev, 0x10, 0x8f82);

/* RemAckCntLimitCtrl = 1 */
__phy_write(phydev, 0x11, 0xfbba);
__phy_write(phydev, 0x12, 0xc3);
__phy_write(phydev, 0x10, 0x87f8);

__mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) |
FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) |
FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) |
FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7));

__mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
REMOTE_ACK_COUNT_LIMIT_CTRL_MASK,
FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1));
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);

/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
Expand Down Expand Up @@ -923,45 +1019,37 @@ static void mt798x_phy_eee(struct phy_device *phydev)
MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);

phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
/* Regsigdet_sel_1000 = 0 */
__phy_write(phydev, 0x11, 0xb);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x9690);

/* REG_EEE_st2TrKf1000 = 2 */
__phy_write(phydev, 0x11, 0x114f);
__phy_write(phydev, 0x12, 0x2);
__phy_write(phydev, 0x10, 0x969a);

/* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
__phy_write(phydev, 0x11, 0x3028);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x969e);

/* RegEEE_slv_wake_int_timer_tar = 8 */
__phy_write(phydev, 0x11, 0x5010);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x96a0);

/* RegEEE_trfreeze_timer2 = 586 */
__phy_write(phydev, 0x11, 0x24a);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x96a8);

/* RegEEE100Stg1_tar = 16 */
__phy_write(phydev, 0x11, 0x3210);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x96b8);

/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
__phy_write(phydev, 0x11, 0x1463);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x96ca);

/* DfeTailEnableVgaThresh1000 = 27 */
__phy_write(phydev, 0x11, 0x36);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x8f80);
__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8,
EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE);

__mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
EEE1000_STAGE2_TR_KF_MASK,
FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2));

__mtk_tr_modify(phydev, 0x2, 0xd, 0xf,
SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK,
FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) |
FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14));

__mtk_tr_modify(phydev, 0x2, 0xd, 0x10,
SLAVE_WAKEINT_TIMER_MASK,
FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8));

__mtk_tr_modify(phydev, 0x2, 0xd, 0x14,
TR_FREEZE_TIMER2_MASK,
FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a));

__mtk_tr_modify(phydev, 0x2, 0xd, 0x1c,
EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
0x10));

__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25,
WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN);

__mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
DFE_TAIL_EANBLE_VGA_TRHESH_1000,
FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b));
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);

phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
Expand Down
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