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dt-bindings: irqchip: Introduce TISCI Interrupt router bindings
Add the DT binding documentation for Interrupt router driver. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
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Texas Instruments K3 Interrupt Router | ||
===================================== | ||
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The Interrupt Router (INTR) module provides a mechanism to mux M | ||
interrupt inputs to N interrupt outputs, where all M inputs are selectable | ||
to be driven per N output. An Interrupt Router can either handle edge triggered | ||
or level triggered interrupts and that is fixed in hardware. | ||
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Interrupt Router | ||
+----------------------+ | ||
| Inputs Outputs | | ||
+-------+ | +------+ +-----+ | | ||
| GPIO |----------->| | irq0 | | 0 | | Host IRQ | ||
+-------+ | +------+ +-----+ | controller | ||
| . . | +-------+ | ||
+-------+ | . . |----->| IRQ | | ||
| INTA |----------->| . . | +-------+ | ||
+-------+ | . +-----+ | | ||
| +------+ | N | | | ||
| | irqM | +-----+ | | ||
| +------+ | | ||
| | | ||
+----------------------+ | ||
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There is one register per output (MUXCNTL_N) that controls the selection. | ||
Configuration of these MUXCNTL_N registers is done by a system controller | ||
(like the Device Memory and Security Controller on K3 AM654 SoC). System | ||
controller will keep track of the used and unused registers within the Router. | ||
Driver should request the system controller to get the range of GIC IRQs | ||
assigned to the requesting hosts. It is the drivers responsibility to keep | ||
track of Host IRQs. | ||
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Communication between the host processor running an OS and the system | ||
controller happens through a protocol called TI System Control Interface | ||
(TISCI protocol). For more details refer: | ||
Documentation/devicetree/bindings/arm/keystone/ti,sci.txt | ||
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TISCI Interrupt Router Node: | ||
---------------------------- | ||
Required Properties: | ||
- compatible: Must be "ti,sci-intr". | ||
- ti,intr-trigger-type: Should be one of the following: | ||
1: If intr supports edge triggered interrupts. | ||
4: If intr supports level triggered interrupts. | ||
- interrupt-controller: Identifies the node as an interrupt controller | ||
- #interrupt-cells: Specifies the number of cells needed to encode an | ||
interrupt source. The value should be 2. | ||
First cell should contain the TISCI device ID of source | ||
Second cell should contain the interrupt source offset | ||
within the device. | ||
- ti,sci: Phandle to TI-SCI compatible System controller node. | ||
- ti,sci-dst-id: TISCI device ID of the destination IRQ controller. | ||
- ti,sci-rm-range-girq: Array of TISCI subtype ids representing the host irqs | ||
assigned to this interrupt router. Each subtype id | ||
corresponds to a range of host irqs. | ||
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For more details on TISCI IRQ resource management refer: | ||
http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html | ||
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Example: | ||
-------- | ||
The following example demonstrates both interrupt router node and the consumer | ||
node(main gpio) on the AM654 SoC: | ||
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main_intr: interrupt-controller0 { | ||
compatible = "ti,sci-intr"; | ||
ti,intr-trigger-type = <1>; | ||
interrupt-controller; | ||
interrupt-parent = <&gic500>; | ||
#interrupt-cells = <2>; | ||
ti,sci = <&dmsc>; | ||
ti,sci-dst-id = <56>; | ||
ti,sci-rm-range-girq = <0x1>; | ||
}; | ||
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main_gpio0: gpio@600000 { | ||
... | ||
interrupt-parent = <&main_intr>; | ||
interrupts = <57 256>, <57 257>, <57 258>, | ||
<57 259>, <57 260>, <57 261>; | ||
... | ||
}; |
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