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devicetree: bindings: IB: Add binding document for Hisilicon RoCE
This patch added DTS binding document for Hisilicon RoCE driver. Signed-off-by: Wei Hu <xavier.huwei@huawei.com> Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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Aug 22, 2016
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Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt
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| Hisilicon RoCE DT description | ||
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| Hisilicon RoCE engine is a part of network subsystem. | ||
| It works depending on other part of network wubsytem, such as, gmac and | ||
| dsa fabric. | ||
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| Additional properties are described here: | ||
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| Required properties: | ||
| - compatible: Should contain "hisilicon,hns-roce-v1". | ||
| - reg: Physical base address of the RoCE driver and | ||
| length of memory mapped region. | ||
| - eth-handle: phandle, specifies a reference to a node | ||
| representing a ethernet device. | ||
| - dsaf-handle: phandle, specifies a reference to a node | ||
| representing a dsaf device. | ||
| - #address-cells: must be 2 | ||
| - #size-cells: must be 2 | ||
| Optional properties: | ||
| - dma-coherent: Present if DMA operations are coherent. | ||
| - interrupt-parent: the interrupt parent of this device. | ||
| - interrupts: should contain 32 completion event irq,1 async event irq | ||
| and 1 event overflow irq. | ||
| - interrupt-names:should be one of 34 irqs for roce device | ||
| - hns-roce-comp-0 ~ hns-roce-comp-31: 32 complete event irq | ||
| - hns-roce-async: 1 async event irq | ||
| - hns-roce-common: named common exception warning irq | ||
| Example: | ||
| infiniband@c4000000 { | ||
| compatible = "hisilicon,hns-roce-v1"; | ||
| reg = <0x0 0xc4000000 0x0 0x100000>; | ||
| dma-coherent; | ||
| eth-handle = <ð2 ð3 ð4 ð5 ð6 ð7>; | ||
| dsaf-handle = <&soc0_dsa>; | ||
| #address-cells = <2>; | ||
| #size-cells = <2>; | ||
| interrupt-parent = <&mbigen_dsa>; | ||
| interrupts = <722 1>, | ||
| <723 1>, | ||
| <724 1>, | ||
| <725 1>, | ||
| <726 1>, | ||
| <727 1>, | ||
| <728 1>, | ||
| <729 1>, | ||
| <730 1>, | ||
| <731 1>, | ||
| <732 1>, | ||
| <733 1>, | ||
| <734 1>, | ||
| <735 1>, | ||
| <736 1>, | ||
| <737 1>, | ||
| <738 1>, | ||
| <739 1>, | ||
| <740 1>, | ||
| <741 1>, | ||
| <742 1>, | ||
| <743 1>, | ||
| <744 1>, | ||
| <745 1>, | ||
| <746 1>, | ||
| <747 1>, | ||
| <748 1>, | ||
| <749 1>, | ||
| <750 1>, | ||
| <751 1>, | ||
| <752 1>, | ||
| <753 1>, | ||
| <785 1>, | ||
| <754 4>; | ||
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| interrupt-names = "hns-roce-comp-0", | ||
| "hns-roce-comp-1", | ||
| "hns-roce-comp-2", | ||
| "hns-roce-comp-3", | ||
| "hns-roce-comp-4", | ||
| "hns-roce-comp-5", | ||
| "hns-roce-comp-6", | ||
| "hns-roce-comp-7", | ||
| "hns-roce-comp-8", | ||
| "hns-roce-comp-9", | ||
| "hns-roce-comp-10", | ||
| "hns-roce-comp-11", | ||
| "hns-roce-comp-12", | ||
| "hns-roce-comp-13", | ||
| "hns-roce-comp-14", | ||
| "hns-roce-comp-15", | ||
| "hns-roce-comp-16", | ||
| "hns-roce-comp-17", | ||
| "hns-roce-comp-18", | ||
| "hns-roce-comp-19", | ||
| "hns-roce-comp-20", | ||
| "hns-roce-comp-21", | ||
| "hns-roce-comp-22", | ||
| "hns-roce-comp-23", | ||
| "hns-roce-comp-24", | ||
| "hns-roce-comp-25", | ||
| "hns-roce-comp-26", | ||
| "hns-roce-comp-27", | ||
| "hns-roce-comp-28", | ||
| "hns-roce-comp-29", | ||
| "hns-roce-comp-30", | ||
| "hns-roce-comp-31", | ||
| "hns-roce-async", | ||
| "hns-roce-common"; | ||
| }; |