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MIPS: generic: Add support for Microsemi Ocelot
Introduce support for the MIPS based Microsemi Ocelot SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Allan Nielsen <Allan.Nielsen@microsemi.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18858/ [jhogan@kernel.org: update ocelot_defconfig specification] Signed-off-by: James Hogan <jhogan@kernel.org>
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Alexandre Belloni
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James Hogan
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Mar 21, 2018
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# require CONFIG_CPU_MIPS32_R2=y | ||
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CONFIG_LEGACY_BOARD_OCELOT=y | ||
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CONFIG_MTD=y | ||
CONFIG_MTD_CMDLINE_PARTS=y | ||
CONFIG_MTD_BLOCK=y | ||
CONFIG_MTD_M25P80=y | ||
CONFIG_MTD_NAND=y | ||
CONFIG_MTD_NAND_PLATFORM=y | ||
CONFIG_MTD_SPI_NOR=y | ||
CONFIG_MTD_UBI=y | ||
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CONFIG_BLK_DEV_LOOP=y | ||
CONFIG_BLK_DEV_RAM=y | ||
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CONFIG_SERIAL_8250=y | ||
CONFIG_SERIAL_8250_CONSOLE=y | ||
CONFIG_SERIAL_OF_PLATFORM=y | ||
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CONFIG_GPIO_SYSFS=y | ||
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CONFIG_I2C=y | ||
CONFIG_I2C_CHARDEV=y | ||
CONFIG_I2C_MUX=y | ||
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CONFIG_SPI=y | ||
CONFIG_SPI_BITBANG=y | ||
CONFIG_SPI_DESIGNWARE=y | ||
CONFIG_SPI_SPIDEV=y | ||
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CONFIG_POWER_RESET=y | ||
CONFIG_POWER_RESET_OCELOT_RESET=y | ||
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CONFIG_MAGIC_SYSRQ=y |
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// SPDX-License-Identifier: (GPL-2.0 OR MIT) | ||
/* | ||
* Microsemi MIPS SoC support | ||
* | ||
* Copyright (c) 2017 Microsemi Corporation | ||
*/ | ||
#include <asm/machine.h> | ||
#include <asm/prom.h> | ||
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#define DEVCPU_GCB_CHIP_REGS_CHIP_ID 0x71070000 | ||
#define CHIP_ID_PART_ID GENMASK(27, 12) | ||
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#define OCELOT_PART_ID (0x7514 << 12) | ||
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#define UART_UART 0x70100000 | ||
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static __init bool ocelot_detect(void) | ||
{ | ||
u32 rev; | ||
int idx; | ||
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/* Look for the TLB entry set up by redboot before trying to use it */ | ||
write_c0_entryhi(DEVCPU_GCB_CHIP_REGS_CHIP_ID); | ||
mtc0_tlbw_hazard(); | ||
tlb_probe(); | ||
tlb_probe_hazard(); | ||
idx = read_c0_index(); | ||
if (idx < 0) | ||
return 0; | ||
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/* A TLB entry exists, lets assume its usable and check the CHIP ID */ | ||
rev = __raw_readl((void __iomem *)DEVCPU_GCB_CHIP_REGS_CHIP_ID); | ||
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if ((rev & CHIP_ID_PART_ID) != OCELOT_PART_ID) | ||
return 0; | ||
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/* Copy command line from bootloader early for Initrd detection */ | ||
if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) { | ||
unsigned int prom_argc = fw_arg0; | ||
const char **prom_argv = (const char **)fw_arg1; | ||
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if (prom_argc > 1 && strlen(prom_argv[1]) > 0) | ||
/* ignore all built-in args if any f/w args given */ | ||
strcpy(arcs_cmdline, prom_argv[1]); | ||
} | ||
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return 1; | ||
} | ||
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static void __init ocelot_earlyprintk_init(void) | ||
{ | ||
void __iomem *uart_base; | ||
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uart_base = ioremap_nocache(UART_UART, 0x20); | ||
setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000); | ||
} | ||
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static void __init ocelot_late_init(void) | ||
{ | ||
ocelot_earlyprintk_init(); | ||
} | ||
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static __init const void *ocelot_fixup_fdt(const void *fdt, | ||
const void *match_data) | ||
{ | ||
/* This has to be done so late because ioremap needs to work */ | ||
late_time_init = ocelot_late_init; | ||
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return fdt; | ||
} | ||
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extern char __dtb_ocelot_pcb123_begin[]; | ||
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MIPS_MACHINE(ocelot) = { | ||
.fdt = __dtb_ocelot_pcb123_begin, | ||
.fixup_fdt = ocelot_fixup_fdt, | ||
.detect = ocelot_detect, | ||
}; |