clk: uniphier: add video input subsystem clock

Add a clock for video input subsystem (EXIV) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
mariux64 · Sep 1, 2017 · 6c26441 · 6c26441
1 parent e3dd205
commit 6c26441
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -65,6 +65,10 @@
 	UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20),		\
 	UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
 
+#define UNIPHIER_LD11_SYS_CLK_EXIV(idx)					\
+	UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10),		\
+	UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
+
 #define UNIPHIER_PRO4_SYS_CLK_ETHER(idx)				\
 	UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
 
@@ -163,6 +167,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
 	UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
 	UNIPHIER_LD11_SYS_CLK_AIO(40),
 	UNIPHIER_LD11_SYS_CLK_EVEA(41),
+	UNIPHIER_LD11_SYS_CLK_EXIV(42),
 	/* CPU gears */
 	UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 	UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
@@ -202,6 +207,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
 	UNIPHIER_LD11_SYS_CLK_AIO(40),
 	UNIPHIER_LD11_SYS_CLK_EVEA(41),
+	UNIPHIER_LD11_SYS_CLK_EXIV(42),
 	/* CPU gears */
 	UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 	UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),