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drm/i915: All fw_domains share the same set/clear/reset values
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Since we reuse the same values for each fw_domain, move them onto
uncore.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170323101944.21627-6-chris@chris-wilson.co.uk
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Chris Wilson committed Mar 23, 2017
1 parent 0f966aa commit 6e3955a
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Showing 2 changed files with 27 additions and 24 deletions.
11 changes: 6 additions & 5 deletions drivers/gpu/drm/i915/i915_drv.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -774,16 +774,17 @@ struct intel_uncore {
enum forcewake_domains fw_domains;
enum forcewake_domains fw_domains_active;

u32 fw_set;
u32 fw_clear;
u32 fw_reset;

struct intel_uncore_forcewake_domain {
enum forcewake_domain_id id;
enum forcewake_domains mask;
unsigned wake_count;
struct hrtimer timer;
i915_reg_t reg_set;
u32 val_set;
u32 val_clear;
i915_reg_t reg_ack;
u32 val_reset;
} fw_domain[FW_DOMAIN_ID_COUNT];

int unclaimed_mmio_check;
Expand Down Expand Up @@ -3956,14 +3957,14 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)

#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
i915_reg_t reg) \
{ \
return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
i915_reg_t reg, uint##x##_t val) \
{ \
write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
Expand Down
40 changes: 21 additions & 19 deletions drivers/gpu/drm/i915/intel_uncore.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,8 +55,7 @@ static inline void
fw_domain_reset(struct drm_i915_private *i915,
const struct intel_uncore_forcewake_domain *d)
{
WARN_ON(!i915_mmio_reg_valid(d->reg_set));
__raw_i915_write32(i915, d->reg_set, d->val_reset);
__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_reset);
}

static inline void
Expand All @@ -70,7 +69,7 @@ fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
}

static inline void
fw_domain_wait_ack_clear(struct drm_i915_private *i915,
fw_domain_wait_ack_clear(const struct drm_i915_private *i915,
const struct intel_uncore_forcewake_domain *d)
{
if (wait_for_atomic((__raw_i915_read32(i915, d->reg_ack) &
Expand All @@ -84,11 +83,11 @@ static inline void
fw_domain_get(struct drm_i915_private *i915,
const struct intel_uncore_forcewake_domain *d)
{
__raw_i915_write32(i915, d->reg_set, d->val_set);
__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_set);
}

static inline void
fw_domain_wait_ack(struct drm_i915_private *i915,
fw_domain_wait_ack(const struct drm_i915_private *i915,
const struct intel_uncore_forcewake_domain *d)
{
if (wait_for_atomic((__raw_i915_read32(i915, d->reg_ack) &
Expand All @@ -99,10 +98,10 @@ fw_domain_wait_ack(struct drm_i915_private *i915,
}

static inline void
fw_domain_put(struct drm_i915_private *i915,
fw_domain_put(const struct drm_i915_private *i915,
const struct intel_uncore_forcewake_domain *d)
{
__raw_i915_write32(i915, d->reg_set, d->val_clear);
__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_clear);
}

static void
Expand Down Expand Up @@ -1139,21 +1138,13 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,

WARN_ON(d->wake_count);

WARN_ON(!i915_mmio_reg_valid(reg_set));
WARN_ON(!i915_mmio_reg_valid(reg_ack));

d->wake_count = 0;
d->reg_set = reg_set;
d->reg_ack = reg_ack;

if (IS_GEN6(dev_priv)) {
d->val_reset = 0;
d->val_set = FORCEWAKE_KERNEL;
d->val_clear = 0;
} else {
/* WaRsClearFWBitsAtReset:bdw,skl */
d->val_reset = _MASKED_BIT_DISABLE(0xffff);
d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
}

d->id = domain_id;

BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
Expand All @@ -1165,7 +1156,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
d->timer.function = intel_uncore_fw_release_timer;

dev_priv->uncore.fw_domains |= (1 << domain_id);
dev_priv->uncore.fw_domains |= BIT(domain_id);

fw_domain_reset(dev_priv, d);
}
Expand All @@ -1175,6 +1166,17 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
return;

if (IS_GEN6(dev_priv)) {
dev_priv->uncore.fw_reset = 0;
dev_priv->uncore.fw_set = FORCEWAKE_KERNEL;
dev_priv->uncore.fw_clear = 0;
} else {
/* WaRsClearFWBitsAtReset:bdw,skl */
dev_priv->uncore.fw_reset = _MASKED_BIT_DISABLE(0xffff);
dev_priv->uncore.fw_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
}

if (IS_GEN9(dev_priv)) {
dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
Expand Down

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