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clk: ralink: mtmips: Fix uninitialized use of ret in mtmips_register_…
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…{fixed,factor}_clocks()

Clang warns:

  drivers/clk/ralink/clk-mtmips.c:309:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
    309 |         return ret;
        |                ^~~
  drivers/clk/ralink/clk-mtmips.c:285:9: note: initialize the variable 'ret' to silence this warning
    285 |         int ret, i;
        |                ^
        |                 = 0
  drivers/clk/ralink/clk-mtmips.c:359:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
    359 |         return ret;
        |                ^~~
  drivers/clk/ralink/clk-mtmips.c:335:9: note: initialize the variable 'ret' to silence this warning
    335 |         int ret, i;
        |                ^
        |                 = 0
  2 errors generated.

Set ret to the return value of clk_hw_register_fixed_rate() using the
PTR_ERR() macro, which ensures ret is not used uninitialized, clearing
up the warning.

Fixes: 6f3b155 ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
Closes: https://github.com/ClangBuiltLinux/linux/issues/1879
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Nathan Chancellor authored and Thomas Bogendoerfer committed Jun 23, 2023
1 parent fd99ac5 commit 6e68dae
Showing 1 changed file with 2 additions and 0 deletions.
2 changes: 2 additions & 0 deletions drivers/clk/ralink/clk-mtmips.c
Original file line number Diff line number Diff line change
Expand Up @@ -292,6 +292,7 @@ static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data,
sclk->parent, 0,
sclk->rate);
if (IS_ERR(sclk->hw)) {
ret = PTR_ERR(sclk->hw);
pr_err("Couldn't register fixed clock %d\n", idx);
goto err_clk_unreg;
}
Expand Down Expand Up @@ -342,6 +343,7 @@ static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
sclk->parent, sclk->flags,
sclk->mult, sclk->div);
if (IS_ERR(sclk->hw)) {
ret = PTR_ERR(sclk->hw);
pr_err("Couldn't register factor clock %d\n", idx);
goto err_clk_unreg;
}
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