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dt-bindings: PCI: microchip: Add Microchip PolarFire host binding
Add device tree bindings for the Microchip PolarFire PCIe controller when configured in host (Root Complex) mode. Link: https://lore.kernel.org/r/20210125162934.5335-3-daire.mcnamara@microchip.com Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org>
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Daire McNamara
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Bjorn Helgaas
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Feb 23, 2021
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Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings | ||
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maintainers: | ||
- Daire McNamara <daire.mcnamara@microchip.com> | ||
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allOf: | ||
- $ref: /schemas/pci/pci-bus.yaml# | ||
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properties: | ||
compatible: | ||
const: microchip,pcie-host-1.0 # PolarFire | ||
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reg: | ||
maxItems: 2 | ||
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reg-names: | ||
items: | ||
- const: cfg | ||
- const: apb | ||
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interrupts: | ||
minItems: 1 | ||
maxItems: 2 | ||
items: | ||
- description: PCIe host controller | ||
- description: builtin MSI controller | ||
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interrupt-names: | ||
minItems: 1 | ||
maxItems: 2 | ||
items: | ||
- const: pcie | ||
- const: msi | ||
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ranges: | ||
maxItems: 1 | ||
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msi-controller: | ||
description: Identifies the node as an MSI controller. | ||
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msi-parent: | ||
description: MSI controller the device is capable of using. | ||
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required: | ||
- reg | ||
- reg-names | ||
- "#interrupt-cells" | ||
- interrupts | ||
- interrupt-map-mask | ||
- interrupt-map | ||
- msi-controller | ||
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unevaluatedProperties: false | ||
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examples: | ||
- | | ||
soc { | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
pcie0: pcie@2030000000 { | ||
compatible = "microchip,pcie-host-1.0"; | ||
reg = <0x0 0x70000000 0x0 0x08000000>, | ||
<0x0 0x43000000 0x0 0x00010000>; | ||
reg-names = "cfg", "apb"; | ||
device_type = "pci"; | ||
#address-cells = <3>; | ||
#size-cells = <2>; | ||
#interrupt-cells = <1>; | ||
interrupts = <119>; | ||
interrupt-map-mask = <0x0 0x0 0x0 0x7>; | ||
interrupt-map = <0 0 0 1 &pcie_intc0 0>, | ||
<0 0 0 2 &pcie_intc0 1>, | ||
<0 0 0 3 &pcie_intc0 2>, | ||
<0 0 0 4 &pcie_intc0 3>; | ||
interrupt-parent = <&plic0>; | ||
msi-parent = <&pcie0>; | ||
msi-controller; | ||
bus-range = <0x00 0x7f>; | ||
ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>; | ||
pcie_intc0: interrupt-controller { | ||
#address-cells = <0>; | ||
#interrupt-cells = <1>; | ||
interrupt-controller; | ||
}; | ||
}; | ||
}; |