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drm/nouveau/clock: pull in the implementation from all over the place
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Still missing the main bits we use to change performance levels, I'll get
to it after all the hard yakka has been finished.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs committed Oct 3, 2012
1 parent 8aceb7d commit 70790f4
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Showing 28 changed files with 1,328 additions and 1,213 deletions.
4 changes: 3 additions & 1 deletion drivers/gpu/drm/nouveau/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -23,11 +23,14 @@ nouveau-y += core/subdev/bios/bit.o
nouveau-y += core/subdev/bios/dcb.o
nouveau-y += core/subdev/bios/gpio.o
nouveau-y += core/subdev/bios/i2c.o
nouveau-y += core/subdev/bios/pll.o
nouveau-y += core/subdev/clock/nv04.o
nouveau-y += core/subdev/clock/nv40.o
nouveau-y += core/subdev/clock/nv50.o
nouveau-y += core/subdev/clock/nva3.o
nouveau-y += core/subdev/clock/nvc0.o
nouveau-y += core/subdev/clock/pllnv04.o
nouveau-y += core/subdev/clock/pllnva3.o
nouveau-y += core/subdev/device/base.o
nouveau-y += core/subdev/device/nv04.o
nouveau-y += core/subdev/device/nv10.o
Expand Down Expand Up @@ -114,7 +117,6 @@ nouveau-y += nouveau_drm.o nouveau_compat.o \
nv50_cursor.o nv50_display.o \
nvd0_display.o \
nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o \
nv50_calc.o \
nv04_pm.o nv40_pm.o nv50_pm.o nva3_pm.o nvc0_pm.o \
nouveau_prime.o

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77 changes: 77 additions & 0 deletions drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,77 @@
#ifndef __NVBIOS_PLL_H__
#define __NVBIOS_PLL_H__

/*XXX: kill me */
struct nouveau_pll_vals {
union {
struct {
#ifdef __BIG_ENDIAN
uint8_t N1, M1, N2, M2;
#else
uint8_t M1, N1, M2, N2;
#endif
};
struct {
uint16_t NM1, NM2;
} __attribute__((packed));
};
int log2P;

int refclk;
};

struct nouveau_bios;

/* these match types in pll limits table version 0x40,
* nouveau uses them on all chipsets internally where a
* specific pll needs to be referenced, but the exact
* register isn't known.
*/
enum nvbios_pll_type {
PLL_CORE = 0x01,
PLL_SHADER = 0x02,
PLL_UNK03 = 0x03,
PLL_MEMORY = 0x04,
PLL_VDEC = 0x05,
PLL_UNK40 = 0x40,
PLL_UNK41 = 0x41,
PLL_UNK42 = 0x42,
PLL_VPLL0 = 0x80,
PLL_VPLL1 = 0x81,
PLL_MAX = 0xff
};

struct nvbios_pll {
enum nvbios_pll_type type;
u32 reg;
u32 refclk;

u8 min_p;
u8 max_p;
u8 bias_p;

/*
* for most pre nv50 cards setting a log2P of 7 (the common max_log2p
* value) is no different to 6 (at least for vplls) so allowing the MNP
* calc to use 7 causes the generated clock to be out by a factor of 2.
* however, max_log2p cannot be fixed-up during parsing as the
* unmodified max_log2p value is still needed for setting mplls, hence
* an additional max_usable_log2p member
*/
u8 max_p_usable;

struct {
u32 min_freq;
u32 max_freq;
u32 min_inputfreq;
u32 max_inputfreq;
u8 min_m;
u8 max_m;
u8 min_n;
u8 max_n;
} vco1, vco2;
};

int nvbios_pll_parse(struct nouveau_bios *, u32 type, struct nvbios_pll *);

#endif
21 changes: 20 additions & 1 deletion drivers/gpu/drm/nouveau/core/include/subdev/clock.h
Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,21 @@
#include <core/device.h>
#include <core/subdev.h>

struct nouveau_pll_vals;
struct nvbios_pll;

struct nouveau_clock {
struct nouveau_subdev base;
void (*pll_set)(struct nouveau_clock *, u32 type, u32 freq);

int (*pll_set)(struct nouveau_clock *, u32 type, u32 freq);

/*XXX: die, these are here *only* to support the completely
* bat-shit insane what-was-nouveau_hw.c code
*/
int (*pll_calc)(struct nouveau_clock *, struct nvbios_pll *,
int clk, struct nouveau_pll_vals *pv);
int (*pll_prog)(struct nouveau_clock *, u32 reg1,
struct nouveau_pll_vals *pv);
};

static inline struct nouveau_clock *
Expand Down Expand Up @@ -37,4 +49,11 @@ extern struct nouveau_oclass nv50_clock_oclass;
extern struct nouveau_oclass nva3_clock_oclass;
extern struct nouveau_oclass nvc0_clock_oclass;

int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq);
int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
int clk, struct nouveau_pll_vals *);
int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
struct nouveau_pll_vals *);


#endif
2 changes: 2 additions & 0 deletions drivers/gpu/drm/nouveau/core/include/subdev/vga.h
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
#ifndef __NOUVEAU_VGA_H__
#define __NOUVEAU_VGA_H__

#include <core/os.h>

/* access to various legacy io ports */
u8 nv_rdport(void *obj, int head, u16 port);
void nv_wrport(void *obj, int head, u16 port, u8 value);
Expand Down
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