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perf vendor events arm64: Categorise the Neoverse V1 counters
This is so they are categorised in the perf list output. The pmus all exist in the armv8-common-and-microarch.json and arm-recommended.json files, so this commit places them into each category's own file under tools/perf/pmu-events/arch/arm64/arm/neoverse-v1 Also add the Neoverse V1 to the arm64 mapfile Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20211006081106.8649-3-andrew.kilroy@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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Arnaldo Carvalho de Melo
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Oct 20, 2021
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,8 @@ | ||
| [ | ||
| { | ||
| "ArchStdEvent": "BR_MIS_PRED" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "BR_PRED" | ||
| } | ||
| ] |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,20 @@ | ||
| [ | ||
| { | ||
| "ArchStdEvent": "CPU_CYCLES" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "BUS_ACCESS" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "BUS_CYCLES" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "BUS_ACCESS_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "BUS_ACCESS_WR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "CNT_CYCLES" | ||
| } | ||
| ] |
155 changes: 155 additions & 0 deletions
155
tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/cache.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,155 @@ | ||
| [ | ||
| { | ||
| "ArchStdEvent": "L1I_CACHE_REFILL" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1I_TLB_REFILL" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_REFILL" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_TLB_REFILL" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1I_CACHE" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_WB" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE_REFILL" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE_WB" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE_ALLOCATE" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_TLB" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1I_TLB" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L3D_CACHE_ALLOCATE" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L3D_CACHE_REFILL" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L3D_CACHE" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_TLB_REFILL" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_TLB" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "DTLB_WALK" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "ITLB_WALK" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "LL_CACHE_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "LL_CACHE_MISS_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_LMISS_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_WR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_REFILL_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_REFILL_WR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_REFILL_INNER" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_WB_VICTIM" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_WB_CLEAN" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_CACHE_INVAL" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_TLB_REFILL_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_TLB_REFILL_WR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_TLB_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1D_TLB_WR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE_WR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE_REFILL_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE_REFILL_WR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE_WB_VICTIM" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE_WB_CLEAN" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE_INVAL" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_TLB_REFILL_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_TLB_REFILL_WR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_TLB_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_TLB_WR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L3D_CACHE_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L1I_CACHE_LMISS" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L2D_CACHE_LMISS_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "L3D_CACHE_LMISS_RD" | ||
| } | ||
| ] |
47 changes: 47 additions & 0 deletions
47
tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/exception.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,47 @@ | ||
| [ | ||
| { | ||
| "ArchStdEvent": "EXC_TAKEN" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "MEMORY_ERROR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_UNDEF" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_SVC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_PABORT" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_DABORT" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_IRQ" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_FIQ" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_SMC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_HVC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_TRAP_PABORT" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_TRAP_DABORT" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_TRAP_OTHER" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_TRAP_IRQ" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_TRAP_FIQ" | ||
| } | ||
| ] |
89 changes: 89 additions & 0 deletions
89
tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/instruction.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,89 @@ | ||
| [ | ||
| { | ||
| "ArchStdEvent": "SW_INCR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "INST_RETIRED" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "EXC_RETURN" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "CID_WRITE_RETIRED" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "INST_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "TTBR_WRITE_RETIRED" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "BR_RETIRED" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "BR_MIS_PRED_RETIRED" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "OP_RETIRED" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "OP_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "LDREX_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "STREX_PASS_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "STREX_FAIL_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "STREX_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "LD_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "ST_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "DP_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "ASE_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "VFP_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "PC_WRITE_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "CRYPTO_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "BR_IMMED_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "BR_RETURN_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "BR_INDIRECT_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "ISB_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "DSB_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "DMB_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "RC_LD_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "RC_ST_SPEC" | ||
| } | ||
| ] |
20 changes: 20 additions & 0 deletions
20
tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/memory.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,20 @@ | ||
| [ | ||
| { | ||
| "ArchStdEvent": "MEM_ACCESS" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "MEM_ACCESS_RD" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "MEM_ACCESS_WR" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "UNALIGNED_LD_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "UNALIGNED_ST_SPEC" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "UNALIGNED_LDST_SPEC" | ||
| } | ||
| ] |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,5 @@ | ||
| [ | ||
| { | ||
| "ArchStdEvent": "REMOTE_ACCESS" | ||
| } | ||
| ] |
23 changes: 23 additions & 0 deletions
23
tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/pipeline.json
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,23 @@ | ||
| [ | ||
| { | ||
| "ArchStdEvent": "STALL_FRONTEND" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "STALL_BACKEND" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "STALL" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "STALL_SLOT_BACKEND" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "STALL_SLOT_FRONTEND" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "STALL_SLOT" | ||
| }, | ||
| { | ||
| "ArchStdEvent": "STALL_BACKEND_MEM" | ||
| } | ||
| ] |
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