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arm64: dts: marvell: add DTS for Turris Mox
This adds support for the Turris Mox board from CZ.NIC. Turris Mox is as modular router based on the Armada 3720 SOC (same as EspressoBin). The basic board can be extended by different modules. If those are connected, U-Boot lets the kernel know via device-tree. Since modules can be connected in different order and some modules can be connected multiple times (up to three modules containing 8-port ethernet switch in DSA configuration can be connected) we decided against using device-tree overlays, because it got complicated rather quickly. (For example the SFP module can be connected directly to the CPU, or after a switch module. There are four cases and all would need different SFP overlay. There are two types of switch modules (8-port with pass-through and 4-port with no pass-through). For those we would again need at least 6 more overlays.) We therefore decided to put all the possibly connected devices in one device-tree and disable them by default. When U-Boot finds out which modules are connected, it fixes the loaded device-tree accordingly just before boot. By Rob Herring's suggestion we also made it so that U-Boot completely removes nodes which are disabled after this fixup. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Rob Herring <robh@kernel.org> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Marek Behún
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Gregory CLEMENT
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Aug 31, 2019
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||
/* | ||
* Device Tree file for CZ.NIC Turris Mox Board | ||
* 2019 by Marek Behun <marek.behun@nic.cz> | ||
*/ | ||
|
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/dts-v1/; | ||
|
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#include <dt-bindings/bus/moxtet.h> | ||
#include <dt-bindings/gpio/gpio.h> | ||
#include <dt-bindings/input/input.h> | ||
#include "armada-372x.dtsi" | ||
|
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/ { | ||
model = "CZ.NIC Turris Mox Board"; | ||
compatible = "cznic,turris-mox", "marvell,armada3720", | ||
"marvell,armada3710"; | ||
|
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aliases { | ||
spi0 = &spi0; | ||
ethernet1 = ð1; | ||
}; | ||
|
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chosen { | ||
stdout-path = "serial0:115200n8"; | ||
}; | ||
|
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memory@0 { | ||
device_type = "memory"; | ||
reg = <0x00000000 0x00000000 0x00000000 0x20000000>; | ||
}; | ||
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leds { | ||
compatible = "gpio-leds"; | ||
red { | ||
label = "mox:red:activity"; | ||
gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; | ||
linux,default-trigger = "default-on"; | ||
}; | ||
}; | ||
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gpio-keys { | ||
compatible = "gpio-keys"; | ||
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reset { | ||
label = "reset"; | ||
linux,code = <KEY_RESTART>; | ||
gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; | ||
debounce-interval = <60>; | ||
}; | ||
}; | ||
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exp_usb3_vbus: usb3-vbus { | ||
compatible = "regulator-fixed"; | ||
regulator-name = "usb3-vbus"; | ||
regulator-min-microvolt = <5000000>; | ||
regulator-max-microvolt = <5000000>; | ||
enable-active-high; | ||
regulator-always-on; | ||
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; | ||
}; | ||
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usb3_phy: usb3-phy { | ||
compatible = "usb-nop-xceiv"; | ||
vcc-supply = <&exp_usb3_vbus>; | ||
}; | ||
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vsdc_reg: vsdc-reg { | ||
compatible = "regulator-gpio"; | ||
regulator-name = "vsdc"; | ||
regulator-min-microvolt = <1800000>; | ||
regulator-max-microvolt = <3300000>; | ||
regulator-boot-on; | ||
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gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; | ||
gpios-states = <0>; | ||
states = <1800000 0x1 | ||
3300000 0x0>; | ||
enable-active-high; | ||
}; | ||
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vsdio_reg: vsdio-reg { | ||
compatible = "regulator-gpio"; | ||
regulator-name = "vsdio"; | ||
regulator-min-microvolt = <1800000>; | ||
regulator-max-microvolt = <3300000>; | ||
regulator-boot-on; | ||
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gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; | ||
gpios-states = <0>; | ||
states = <1800000 0x1 | ||
3300000 0x0>; | ||
enable-active-high; | ||
}; | ||
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sdhci1_pwrseq: sdhci1-pwrseq { | ||
compatible = "mmc-pwrseq-simple"; | ||
reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; | ||
status = "okay"; | ||
}; | ||
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sfp: sfp { | ||
compatible = "sff,sfp+"; | ||
i2c-bus = <&i2c0>; | ||
los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; | ||
tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; | ||
mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; | ||
tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; | ||
rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; | ||
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/* enabled by U-Boot if SFP module is present */ | ||
status = "disabled"; | ||
}; | ||
}; | ||
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&i2c0 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&i2c1_pins>; | ||
clock-frequency = <100000>; | ||
status = "okay"; | ||
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rtc@6f { | ||
compatible = "microchip,mcp7940x"; | ||
reg = <0x6f>; | ||
}; | ||
}; | ||
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&pcie_reset_pins { | ||
function = "gpio"; | ||
}; | ||
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&pcie0 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; | ||
status = "okay"; | ||
max-link-speed = <2>; | ||
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; | ||
phys = <&comphy1 0>; | ||
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/* enabled by U-Boot if PCIe module is present */ | ||
status = "disabled"; | ||
}; | ||
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&uart0 { | ||
status = "okay"; | ||
}; | ||
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ð0 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&rgmii_pins>; | ||
phy-mode = "rgmii-id"; | ||
phy = <&phy1>; | ||
status = "okay"; | ||
}; | ||
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ð1 { | ||
phy-mode = "2500base-x"; | ||
managed = "in-band-status"; | ||
phys = <&comphy0 1>; | ||
}; | ||
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&sdhci0 { | ||
wp-inverted; | ||
bus-width = <4>; | ||
cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; | ||
vqmmc-supply = <&vsdc_reg>; | ||
marvell,pad-type = "sd"; | ||
status = "okay"; | ||
}; | ||
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&sdhci1 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&sdio_pins>; | ||
non-removable; | ||
bus-width = <4>; | ||
marvell,pad-type = "sd"; | ||
vqmmc-supply = <&vsdio_reg>; | ||
mmc-pwrseq = <&sdhci1_pwrseq>; | ||
status = "okay"; | ||
}; | ||
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&spi0 { | ||
status = "okay"; | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; | ||
assigned-clocks = <&nb_periph_clk 7>; | ||
assigned-clock-parents = <&tbg 1>; | ||
assigned-clock-rates = <20000000>; | ||
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spi-flash@0 { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
compatible = "jedec,spi-nor"; | ||
reg = <0>; | ||
spi-max-frequency = <20000000>; | ||
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partitions { | ||
compatible = "fixed-partitions"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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partition@0 { | ||
label = "secure-firmware"; | ||
reg = <0x0 0x20000>; | ||
}; | ||
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partition@20000 { | ||
label = "u-boot"; | ||
reg = <0x20000 0x160000>; | ||
}; | ||
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partition@180000 { | ||
label = "u-boot-env"; | ||
reg = <0x180000 0x10000>; | ||
}; | ||
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partition@190000 { | ||
label = "Rescue system"; | ||
reg = <0x190000 0x660000>; | ||
}; | ||
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partition@7f0000 { | ||
label = "dtb"; | ||
reg = <0x7f0000 0x10000>; | ||
}; | ||
}; | ||
}; | ||
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moxtet: moxtet@1 { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
compatible = "cznic,moxtet"; | ||
reg = <1>; | ||
reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; | ||
spi-max-frequency = <10000000>; | ||
spi-cpol; | ||
spi-cpha; | ||
interrupt-controller; | ||
#interrupt-cells = <1>; | ||
interrupt-parent = <&gpiosb>; | ||
interrupts = <5 IRQ_TYPE_EDGE_FALLING>; | ||
status = "okay"; | ||
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moxtet_sfp: gpio@0 { | ||
compatible = "cznic,moxtet-gpio"; | ||
gpio-controller; | ||
#gpio-cells = <2>; | ||
reg = <0>; | ||
status = "disabled"; | ||
}; | ||
}; | ||
}; | ||
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&usb2 { | ||
status = "okay"; | ||
}; | ||
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&usb3 { | ||
status = "okay"; | ||
phys = <&comphy2 0>; | ||
usb-phy = <&usb3_phy>; | ||
}; | ||
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&mdio { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&smi_pins>; | ||
status = "okay"; | ||
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phy1: ethernet-phy@1 { | ||
reg = <1>; | ||
}; | ||
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/* switch nodes are enabled by U-Boot if modules are present */ | ||
switch0@10 { | ||
compatible = "marvell,mv88e6190"; | ||
reg = <0x10 0>; | ||
dsa,member = <0 0>; | ||
interrupt-parent = <&moxtet>; | ||
interrupts = <MOXTET_IRQ_PERIDOT(0)>; | ||
status = "disabled"; | ||
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mdio { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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switch0phy1: switch0phy1@1 { | ||
reg = <0x1>; | ||
}; | ||
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switch0phy2: switch0phy2@2 { | ||
reg = <0x2>; | ||
}; | ||
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switch0phy3: switch0phy3@3 { | ||
reg = <0x3>; | ||
}; | ||
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switch0phy4: switch0phy4@4 { | ||
reg = <0x4>; | ||
}; | ||
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switch0phy5: switch0phy5@5 { | ||
reg = <0x5>; | ||
}; | ||
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switch0phy6: switch0phy6@6 { | ||
reg = <0x6>; | ||
}; | ||
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switch0phy7: switch0phy7@7 { | ||
reg = <0x7>; | ||
}; | ||
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switch0phy8: switch0phy8@8 { | ||
reg = <0x8>; | ||
}; | ||
}; | ||
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ports { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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port@1 { | ||
reg = <0x1>; | ||
label = "lan1"; | ||
phy-handle = <&switch0phy1>; | ||
}; | ||
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port@2 { | ||
reg = <0x2>; | ||
label = "lan2"; | ||
phy-handle = <&switch0phy2>; | ||
}; | ||
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port@3 { | ||
reg = <0x3>; | ||
label = "lan3"; | ||
phy-handle = <&switch0phy3>; | ||
}; | ||
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port@4 { | ||
reg = <0x4>; | ||
label = "lan4"; | ||
phy-handle = <&switch0phy4>; | ||
}; | ||
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port@5 { | ||
reg = <0x5>; | ||
label = "lan5"; | ||
phy-handle = <&switch0phy5>; | ||
}; | ||
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port@6 { | ||
reg = <0x6>; | ||
label = "lan6"; | ||
phy-handle = <&switch0phy6>; | ||
}; | ||
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port@7 { | ||
reg = <0x7>; | ||
label = "lan7"; | ||
phy-handle = <&switch0phy7>; | ||
}; | ||
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port@8 { | ||
reg = <0x8>; | ||
label = "lan8"; | ||
phy-handle = <&switch0phy8>; | ||
}; | ||
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port@9 { | ||
reg = <0x9>; | ||
label = "cpu"; | ||
ethernet = <ð1>; | ||
phy-mode = "2500base-x"; | ||
managed = "in-band-status"; | ||
}; | ||
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switch0port10: port@a { | ||
reg = <0xa>; | ||
label = "dsa"; | ||
phy-mode = "2500base-x"; | ||
managed = "in-band-status"; | ||
link = <&switch1port9 &switch2port9>; | ||
status = "disabled"; | ||
}; | ||
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port-sfp@a { | ||
reg = <0xa>; | ||
label = "sfp"; | ||
sfp = <&sfp>; | ||
phy-mode = "sgmii"; | ||
managed = "in-band-status"; | ||
status = "disabled"; | ||
}; | ||
}; | ||
}; | ||
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switch0@2 { | ||
compatible = "marvell,mv88e6085"; | ||
reg = <0x2 0>; | ||
dsa,member = <0 0>; | ||
interrupt-parent = <&moxtet>; | ||
interrupts = <MOXTET_IRQ_TOPAZ>; | ||
status = "disabled"; | ||
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mdio { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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switch0phy1_topaz: switch0phy1@11 { | ||
reg = <0x11>; | ||
}; | ||
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switch0phy2_topaz: switch0phy2@12 { | ||
reg = <0x12>; | ||
}; | ||
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switch0phy3_topaz: switch0phy3@13 { | ||
reg = <0x13>; | ||
}; | ||
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switch0phy4_topaz: switch0phy4@14 { | ||
reg = <0x14>; | ||
}; | ||
}; | ||
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ports { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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port@1 { | ||
reg = <0x1>; | ||
label = "lan1"; | ||
phy-handle = <&switch0phy1_topaz>; | ||
}; | ||
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port@2 { | ||
reg = <0x2>; | ||
label = "lan2"; | ||
phy-handle = <&switch0phy2_topaz>; | ||
}; | ||
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port@3 { | ||
reg = <0x3>; | ||
label = "lan3"; | ||
phy-handle = <&switch0phy3_topaz>; | ||
}; | ||
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port@4 { | ||
reg = <0x4>; | ||
label = "lan4"; | ||
phy-handle = <&switch0phy4_topaz>; | ||
}; | ||
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port@5 { | ||
reg = <0x5>; | ||
label = "cpu"; | ||
phy-mode = "2500base-x"; | ||
managed = "in-band-status"; | ||
ethernet = <ð1>; | ||
}; | ||
}; | ||
}; | ||
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switch1@11 { | ||
compatible = "marvell,mv88e6190"; | ||
reg = <0x11 0>; | ||
dsa,member = <0 1>; | ||
interrupt-parent = <&moxtet>; | ||
interrupts = <MOXTET_IRQ_PERIDOT(1)>; | ||
status = "disabled"; | ||
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mdio { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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switch1phy1: switch1phy1@1 { | ||
reg = <0x1>; | ||
}; | ||
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switch1phy2: switch1phy2@2 { | ||
reg = <0x2>; | ||
}; | ||
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switch1phy3: switch1phy3@3 { | ||
reg = <0x3>; | ||
}; | ||
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switch1phy4: switch1phy4@4 { | ||
reg = <0x4>; | ||
}; | ||
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switch1phy5: switch1phy5@5 { | ||
reg = <0x5>; | ||
}; | ||
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switch1phy6: switch1phy6@6 { | ||
reg = <0x6>; | ||
}; | ||
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switch1phy7: switch1phy7@7 { | ||
reg = <0x7>; | ||
}; | ||
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switch1phy8: switch1phy8@8 { | ||
reg = <0x8>; | ||
}; | ||
}; | ||
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ports { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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port@1 { | ||
reg = <0x1>; | ||
label = "lan9"; | ||
phy-handle = <&switch1phy1>; | ||
}; | ||
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port@2 { | ||
reg = <0x2>; | ||
label = "lan10"; | ||
phy-handle = <&switch1phy2>; | ||
}; | ||
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port@3 { | ||
reg = <0x3>; | ||
label = "lan11"; | ||
phy-handle = <&switch1phy3>; | ||
}; | ||
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port@4 { | ||
reg = <0x4>; | ||
label = "lan12"; | ||
phy-handle = <&switch1phy4>; | ||
}; | ||
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port@5 { | ||
reg = <0x5>; | ||
label = "lan13"; | ||
phy-handle = <&switch1phy5>; | ||
}; | ||
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port@6 { | ||
reg = <0x6>; | ||
label = "lan14"; | ||
phy-handle = <&switch1phy6>; | ||
}; | ||
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port@7 { | ||
reg = <0x7>; | ||
label = "lan15"; | ||
phy-handle = <&switch1phy7>; | ||
}; | ||
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port@8 { | ||
reg = <0x8>; | ||
label = "lan16"; | ||
phy-handle = <&switch1phy8>; | ||
}; | ||
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switch1port9: port@9 { | ||
reg = <0x9>; | ||
label = "dsa"; | ||
phy-mode = "2500base-x"; | ||
managed = "in-band-status"; | ||
link = <&switch0port10>; | ||
}; | ||
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switch1port10: port@a { | ||
reg = <0xa>; | ||
label = "dsa"; | ||
phy-mode = "2500base-x"; | ||
managed = "in-band-status"; | ||
link = <&switch2port9>; | ||
status = "disabled"; | ||
}; | ||
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port-sfp@a { | ||
reg = <0xa>; | ||
label = "sfp"; | ||
sfp = <&sfp>; | ||
phy-mode = "sgmii"; | ||
managed = "in-band-status"; | ||
status = "disabled"; | ||
}; | ||
}; | ||
}; | ||
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switch1@2 { | ||
compatible = "marvell,mv88e6085"; | ||
reg = <0x2 0>; | ||
dsa,member = <0 1>; | ||
interrupt-parent = <&moxtet>; | ||
interrupts = <MOXTET_IRQ_TOPAZ>; | ||
status = "disabled"; | ||
|
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mdio { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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switch1phy1_topaz: switch1phy1@11 { | ||
reg = <0x11>; | ||
}; | ||
|
||
switch1phy2_topaz: switch1phy2@12 { | ||
reg = <0x12>; | ||
}; | ||
|
||
switch1phy3_topaz: switch1phy3@13 { | ||
reg = <0x13>; | ||
}; | ||
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||
switch1phy4_topaz: switch1phy4@14 { | ||
reg = <0x14>; | ||
}; | ||
}; | ||
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ports { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
|
||
port@1 { | ||
reg = <0x1>; | ||
label = "lan9"; | ||
phy-handle = <&switch1phy1_topaz>; | ||
}; | ||
|
||
port@2 { | ||
reg = <0x2>; | ||
label = "lan10"; | ||
phy-handle = <&switch1phy2_topaz>; | ||
}; | ||
|
||
port@3 { | ||
reg = <0x3>; | ||
label = "lan11"; | ||
phy-handle = <&switch1phy3_topaz>; | ||
}; | ||
|
||
port@4 { | ||
reg = <0x4>; | ||
label = "lan12"; | ||
phy-handle = <&switch1phy4_topaz>; | ||
}; | ||
|
||
port@5 { | ||
reg = <0x5>; | ||
label = "dsa"; | ||
phy-mode = "2500base-x"; | ||
managed = "in-band-status"; | ||
link = <&switch0port10>; | ||
}; | ||
}; | ||
}; | ||
|
||
switch2@12 { | ||
compatible = "marvell,mv88e6190"; | ||
reg = <0x12 0>; | ||
dsa,member = <0 2>; | ||
interrupt-parent = <&moxtet>; | ||
interrupts = <MOXTET_IRQ_PERIDOT(2)>; | ||
status = "disabled"; | ||
|
||
mdio { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
|
||
switch2phy1: switch2phy1@1 { | ||
reg = <0x1>; | ||
}; | ||
|
||
switch2phy2: switch2phy2@2 { | ||
reg = <0x2>; | ||
}; | ||
|
||
switch2phy3: switch2phy3@3 { | ||
reg = <0x3>; | ||
}; | ||
|
||
switch2phy4: switch2phy4@4 { | ||
reg = <0x4>; | ||
}; | ||
|
||
switch2phy5: switch2phy5@5 { | ||
reg = <0x5>; | ||
}; | ||
|
||
switch2phy6: switch2phy6@6 { | ||
reg = <0x6>; | ||
}; | ||
|
||
switch2phy7: switch2phy7@7 { | ||
reg = <0x7>; | ||
}; | ||
|
||
switch2phy8: switch2phy8@8 { | ||
reg = <0x8>; | ||
}; | ||
}; | ||
|
||
ports { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
|
||
port@1 { | ||
reg = <0x1>; | ||
label = "lan17"; | ||
phy-handle = <&switch2phy1>; | ||
}; | ||
|
||
port@2 { | ||
reg = <0x2>; | ||
label = "lan18"; | ||
phy-handle = <&switch2phy2>; | ||
}; | ||
|
||
port@3 { | ||
reg = <0x3>; | ||
label = "lan19"; | ||
phy-handle = <&switch2phy3>; | ||
}; | ||
|
||
port@4 { | ||
reg = <0x4>; | ||
label = "lan20"; | ||
phy-handle = <&switch2phy4>; | ||
}; | ||
|
||
port@5 { | ||
reg = <0x5>; | ||
label = "lan21"; | ||
phy-handle = <&switch2phy5>; | ||
}; | ||
|
||
port@6 { | ||
reg = <0x6>; | ||
label = "lan22"; | ||
phy-handle = <&switch2phy6>; | ||
}; | ||
|
||
port@7 { | ||
reg = <0x7>; | ||
label = "lan23"; | ||
phy-handle = <&switch2phy7>; | ||
}; | ||
|
||
port@8 { | ||
reg = <0x8>; | ||
label = "lan24"; | ||
phy-handle = <&switch2phy8>; | ||
}; | ||
|
||
switch2port9: port@9 { | ||
reg = <0x9>; | ||
label = "dsa"; | ||
phy-mode = "2500base-x"; | ||
managed = "in-band-status"; | ||
link = <&switch1port10 &switch0port10>; | ||
}; | ||
|
||
port-sfp@a { | ||
reg = <0xa>; | ||
label = "sfp"; | ||
sfp = <&sfp>; | ||
phy-mode = "sgmii"; | ||
managed = "in-band-status"; | ||
status = "disabled"; | ||
}; | ||
}; | ||
}; | ||
|
||
switch2@2 { | ||
compatible = "marvell,mv88e6085"; | ||
reg = <0x2 0>; | ||
dsa,member = <0 2>; | ||
interrupt-parent = <&moxtet>; | ||
interrupts = <MOXTET_IRQ_TOPAZ>; | ||
status = "disabled"; | ||
|
||
mdio { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
|
||
switch2phy1_topaz: switch2phy1@11 { | ||
reg = <0x11>; | ||
}; | ||
|
||
switch2phy2_topaz: switch2phy2@12 { | ||
reg = <0x12>; | ||
}; | ||
|
||
switch2phy3_topaz: switch2phy3@13 { | ||
reg = <0x13>; | ||
}; | ||
|
||
switch2phy4_topaz: switch2phy4@14 { | ||
reg = <0x14>; | ||
}; | ||
}; | ||
|
||
ports { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
|
||
port@1 { | ||
reg = <0x1>; | ||
label = "lan17"; | ||
phy-handle = <&switch2phy1_topaz>; | ||
}; | ||
|
||
port@2 { | ||
reg = <0x2>; | ||
label = "lan18"; | ||
phy-handle = <&switch2phy2_topaz>; | ||
}; | ||
|
||
port@3 { | ||
reg = <0x3>; | ||
label = "lan19"; | ||
phy-handle = <&switch2phy3_topaz>; | ||
}; | ||
|
||
port@4 { | ||
reg = <0x4>; | ||
label = "lan20"; | ||
phy-handle = <&switch2phy4_topaz>; | ||
}; | ||
|
||
port@5 { | ||
reg = <0x5>; | ||
label = "dsa"; | ||
phy-mode = "2500base-x"; | ||
managed = "in-band-status"; | ||
link = <&switch1port10 &switch0port10>; | ||
}; | ||
}; | ||
}; | ||
}; |