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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/gi…
…t/arm/arm-soc
Pull ARM SoC device tree updates from Olof Johansson:
"As always, a large number of DT updates. Too many to enumerate them
all, but at a glance:
New SoCs introduced in this release:
- Amlogic:
+ Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some
set top boxes and other products.
- Mediatek:
+ MT7623A, which is a flavor of the MT7623 family with other
on-chip ethernet options.
- Qualcomm:
+ SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845
(Cortex-A75/A55 derivative) SoC that's one of the current
high-end mobile SoCs.
It's great to see mainline support for it. So far, you can't do
much with it, since a lot of peripherals are not yet in the DTs
but driver support for USB, GPU and other pieces are starting to
trickle in. This might end up being a well-supported SoC
upstream if the momentum keeps up.
- Renesas:
+ R8A77990, a.k.a R-Car E3, a new automotive
entertainment-targeted SoC. Currently only one Cortex-A53 CPU is
enabled, we are eagerly awaiting more. So far, basic drivers
such as serial, gpios, PMU and ethernet are enabled.
+ R8A77470, a.k.a. RZ/G1C, a new dual Cortex-A7 SoC with PowerVR
GPU. Same here, basic set of drivers such as serial, gpios and
ethernet enabled, and SMP support is also forthcoming.
- STMicroelectronics:
+ STM32F469, very similar tih STM32F429 but with display support
Enhancements to SoCs/platforms (DTS contents, some driver portions
might not be in yet):
- Allwinner sun8i (h3/a33/a83t) SMP, DVFS tweaks, misc
- Amlogic Meson: I2C, UFS, TDM, GPIO external interrupts, MMC resets
- Hisilicon hi3660: Thermal cooling, CPU frequency scaling, mailbox interfaces
- Marvell Berlin2CD: SMP support, thermal sensors
- Mediatek MT7623: Highspeed DMA, audio support
- Qualcomm IPQ8074 PCIe support, MSM8996 UFS support
- Renesas: Watchdog and PMU support across many platforms
- Rockchip RK3399: USB3 OTG support
- Samsung Exynos: Audio-over-HDMI on Odroid X/X2/U3
- STMicro STM32: Lots of peripherals added to STM32MP175C
- Uniphier: Ethernet support
New boards:
- Allwinner A20: Olimex A20-SOM-EVB-eMMC variant
- Allwinner H2+: Libre Computer ALL-H3-CC (h2+ version)
- Allwinner A33: Nintendo NES/SuperNES Classic Edition
- Aspeed: S2600WF, Inventec Lanyang BMC, Portwell Neptune
- Berlin2CD: Valve Steam Link
- Broadcom BCM5301X: Luxul XAP-1610 and XWR-3150 V1
- Broadcom: Raspberry Pi 3 B+
- Mediatek MT7623N and MT7623A: reference boards
- Meson 8M2: Tronsmart MXIII Plus
- NXP i.MX: Engicam i.CoreM6, DHCOM iMX6 SOM, BTicino i.MX6DL Mamoj
- Qualcomm MSM8974: Sony Xperia Z1 Compact support
- Qualcomm SDM845: MTP development board
- Renesas: Ebisu R8A77990 board
- Renesas RZ/G1C: iwg23s: iWave G235-SDB
- TI am335x: Pocketbeagle support"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (448 commits)
ARM: dts: aspeed: Fix hwrng register address
arm64: dts: sprd: whale2: Add the rtc enable clock for watchdog
arm64: dts: sprd: Add GPIO and GPIO keys device nodes
arm64: dts: sprd: fix typo in 'remote-endpoint'
arm64: dts: apq8096-db820c: Removed bt-en-1-8v regulator
arm64: dts: fix regulator property name for wlan pcie endpoint
arm64: dts: qcom: msm8996: Use UFS_GDSC for UFS
ARM: dts: pxa3xx: fix MMC clocks
ARM: pxa: dts: add pin definitions for extended GPIOs
ARM: pxa: dts: add gpio-ranges to gpio controller
ARM: dts: ipq8074: Enable few peripherals for hk01 board
ARM: dts: ipq8074: Add pcie nodes
ARM: dts: ipq8074: Add peripheral nodes
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
ARM: dts: ipq4019: Change the max opp frequency
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18
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt
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37
Documentation/devicetree/bindings/reserved-memory/qcom,cmd-db.txt
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,37 @@ | ||
| Command DB | ||
| --------- | ||
|
|
||
| Command DB is a database that provides a mapping between resource key and the | ||
| resource address for a system resource managed by a remote processor. The data | ||
| is stored in a shared memory region and is loaded by the remote processor. | ||
|
|
||
| Some of the Qualcomm Technologies Inc SoC's have hardware accelerators for | ||
| controlling shared resources. Depending on the board configuration the shared | ||
| resource properties may change. These properties are dynamically probed by the | ||
| remote processor and made available in the shared memory. | ||
|
|
||
| The bindings for Command DB is specified in the reserved-memory section in | ||
| devicetree. The devicetree representation of the command DB driver should be: | ||
|
|
||
| Properties: | ||
| - compatible: | ||
| Usage: required | ||
| Value type: <string> | ||
| Definition: Should be "qcom,cmd-db" | ||
|
|
||
| - reg: | ||
| Usage: required | ||
| Value type: <prop encoded array> | ||
| Definition: The register address that points to the actual location of | ||
| the Command DB in memory. | ||
|
|
||
| Example: | ||
|
|
||
| reserved-memory { | ||
| [...] | ||
| reserved-memory@85fe0000 { | ||
| reg = <0x0 0x85fe0000 0x0 0x20000>; | ||
| compatible = "qcom,cmd-db"; | ||
| no-map; | ||
| }; | ||
| }; |
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119
Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
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| Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller | ||
|
|
||
| Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper | ||
| is a programmable module for supporting a wide range of serial interfaces | ||
| like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial | ||
| Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP | ||
| Wrapper controller is modeled as a node with zero or more child nodes each | ||
| representing a serial engine. | ||
|
|
||
| Required properties: | ||
| - compatible: Must be "qcom,geni-se-qup". | ||
| - reg: Must contain QUP register address and length. | ||
| - clock-names: Must contain "m-ahb" and "s-ahb". | ||
| - clocks: AHB clocks needed by the device. | ||
|
|
||
| Required properties if child node exists: | ||
| - #address-cells: Must be <1> for Serial Engine Address | ||
| - #size-cells: Must be <1> for Serial Engine Address Size | ||
| - ranges: Must be present | ||
|
|
||
| Properties for children: | ||
|
|
||
| A GENI based QUP wrapper controller node can contain 0 or more child nodes | ||
| representing serial devices. These serial devices can be a QCOM UART, I2C | ||
| controller, SPI controller, or some combination of aforementioned devices. | ||
| Please refer below the child node definitions for the supported serial | ||
| interface protocols. | ||
|
|
||
| Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller | ||
|
|
||
| Required properties: | ||
| - compatible: Must be "qcom,geni-i2c". | ||
| - reg: Must contain QUP register address and length. | ||
| - interrupts: Must contain I2C interrupt. | ||
| - clock-names: Must contain "se". | ||
| - clocks: Serial engine core clock needed by the device. | ||
| - #address-cells: Must be <1> for I2C device address. | ||
| - #size-cells: Must be <0> as I2C addresses have no size component. | ||
|
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||
| Optional property: | ||
| - clock-frequency: Desired I2C bus clock frequency in Hz. | ||
| When missing default to 400000Hz. | ||
|
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||
| Child nodes should conform to I2C bus binding as described in i2c.txt. | ||
|
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||
| Qualcomm Technologies Inc. GENI Serial Engine based UART Controller | ||
|
|
||
| Required properties: | ||
| - compatible: Must be "qcom,geni-debug-uart". | ||
| - reg: Must contain UART register location and length. | ||
| - interrupts: Must contain UART core interrupts. | ||
| - clock-names: Must contain "se". | ||
| - clocks: Serial engine core clock needed by the device. | ||
|
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||
| Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller | ||
|
|
||
| Required properties: | ||
| - compatible: Must contain "qcom,geni-spi". | ||
| - reg: Must contain SPI register location and length. | ||
| - interrupts: Must contain SPI controller interrupts. | ||
| - clock-names: Must contain "se". | ||
| - clocks: Serial engine core clock needed by the device. | ||
| - spi-max-frequency: Specifies maximum SPI clock frequency, units - Hz. | ||
| - #address-cells: Must be <1> to define a chip select address on | ||
| the SPI bus. | ||
| - #size-cells: Must be <0>. | ||
|
|
||
| SPI slave nodes must be children of the SPI master node and conform to SPI bus | ||
| binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. | ||
|
|
||
| Example: | ||
| geniqup@8c0000 { | ||
| compatible = "qcom,geni-se-qup"; | ||
| reg = <0x8c0000 0x6000>; | ||
| clock-names = "m-ahb", "s-ahb"; | ||
| clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, | ||
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| ranges; | ||
|
|
||
| i2c0: i2c@a94000 { | ||
| compatible = "qcom,geni-i2c"; | ||
| reg = <0xa94000 0x4000>; | ||
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-names = "se"; | ||
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>; | ||
| pinctrl-names = "default", "sleep"; | ||
| pinctrl-0 = <&qup_1_i2c_5_active>; | ||
| pinctrl-1 = <&qup_1_i2c_5_sleep>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| }; | ||
|
|
||
| uart0: serial@a88000 { | ||
| compatible = "qcom,geni-debug-uart"; | ||
| reg = <0xa88000 0x7000>; | ||
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-names = "se"; | ||
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; | ||
| pinctrl-names = "default", "sleep"; | ||
| pinctrl-0 = <&qup_1_uart_3_active>; | ||
| pinctrl-1 = <&qup_1_uart_3_sleep>; | ||
| }; | ||
|
|
||
| spi0: spi@a84000 { | ||
| compatible = "qcom,geni-spi"; | ||
| reg = <0xa84000 0x4000>; | ||
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | ||
| clock-names = "se"; | ||
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; | ||
| pinctrl-names = "default", "sleep"; | ||
| pinctrl-0 = <&qup_1_spi_2_active>; | ||
| pinctrl-1 = <&qup_1_spi_2_sleep>; | ||
| spi-max-frequency = <19200000>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| }; | ||
| } |
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