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powerpc: Remove core support for 40x
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Now that 40x platforms have gone, remove support
for 40x in the core of powerpc arch.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20240628121201.130802-4-mpe@ellerman.id.au
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Christophe Leroy authored and Michael Ellerman committed Jun 28, 2024
1 parent e939da8 commit 732b32d
Showing 29 changed files with 14 additions and 1,728 deletions.
7 changes: 0 additions & 7 deletions arch/powerpc/include/asm/cputable.h
Original file line number Diff line number Diff line change
@@ -353,7 +353,6 @@ static inline void cpu_feature_keys_init(void) { }
CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE)
#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
#define CPU_FTRS_40X (CPU_FTR_NOEXECUTE)
#define CPU_FTRS_44X (CPU_FTR_NOEXECUTE)
#define CPU_FTRS_440x6 (CPU_FTR_NOEXECUTE | \
CPU_FTR_INDEXED_DCR)
@@ -507,9 +506,6 @@ enum {
#ifdef CONFIG_PPC_8xx
CPU_FTRS_8XX |
#endif
#ifdef CONFIG_40x
CPU_FTRS_40X |
#endif
#ifdef CONFIG_PPC_47x
CPU_FTRS_47X | CPU_FTR_476_DD2 |
#elif defined(CONFIG_44x)
@@ -582,9 +578,6 @@ enum {
#ifdef CONFIG_PPC_8xx
CPU_FTRS_8XX &
#endif
#ifdef CONFIG_40x
CPU_FTRS_40X &
#endif
#ifdef CONFIG_PPC_47x
CPU_FTRS_47X &
#elif defined(CONFIG_44x)
7 changes: 0 additions & 7 deletions arch/powerpc/include/asm/mmu.h
Original file line number Diff line number Diff line change
@@ -16,7 +16,6 @@
*/
#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
@@ -153,9 +152,6 @@ enum {
#ifdef CONFIG_PPC_8xx
MMU_FTR_TYPE_8xx |
#endif
#ifdef CONFIG_40x
MMU_FTR_TYPE_40x |
#endif
#ifdef CONFIG_PPC_47x
MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL |
#elif defined(CONFIG_44x)
@@ -202,9 +198,6 @@ enum {
#ifdef CONFIG_PPC_8xx
#define MMU_FTRS_ALWAYS MMU_FTR_TYPE_8xx
#endif
#ifdef CONFIG_40x
#define MMU_FTRS_ALWAYS MMU_FTR_TYPE_40x
#endif
#ifdef CONFIG_PPC_47x
#define MMU_FTRS_ALWAYS MMU_FTR_TYPE_47x
#elif defined(CONFIG_44x)
68 changes: 0 additions & 68 deletions arch/powerpc/include/asm/nohash/32/mmu-40x.h

This file was deleted.

4 changes: 1 addition & 3 deletions arch/powerpc/include/asm/nohash/32/pgtable.h
Original file line number Diff line number Diff line change
@@ -118,9 +118,7 @@
* (hardware-defined) PowerPC PTE as closely as possible.
*/

#if defined(CONFIG_40x)
#include <asm/nohash/32/pte-40x.h>
#elif defined(CONFIG_44x)
#if defined(CONFIG_44x)
#include <asm/nohash/32/pte-44x.h>
#elif defined(CONFIG_PPC_85xx) && defined(CONFIG_PTE_64BIT)
#include <asm/nohash/pte-e500.h>
73 changes: 0 additions & 73 deletions arch/powerpc/include/asm/nohash/32/pte-40x.h

This file was deleted.

5 changes: 1 addition & 4 deletions arch/powerpc/include/asm/nohash/mmu.h
Original file line number Diff line number Diff line change
@@ -2,10 +2,7 @@
#ifndef _ASM_POWERPC_NOHASH_MMU_H_
#define _ASM_POWERPC_NOHASH_MMU_H_

#if defined(CONFIG_40x)
/* 40x-style software loaded TLB */
#include <asm/nohash/32/mmu-40x.h>
#elif defined(CONFIG_44x)
#if defined(CONFIG_44x)
/* 44x-style software loaded TLB */
#include <asm/nohash/32/mmu-44x.h>
#elif defined(CONFIG_PPC_E500)
25 changes: 1 addition & 24 deletions arch/powerpc/include/asm/reg.h
Original file line number Diff line number Diff line change
@@ -233,14 +233,10 @@

/* Special Purpose Registers (SPRNs)*/

#ifdef CONFIG_40x
#define SPRN_PID 0x3B1 /* Process ID */
#else
#define SPRN_PID 0x030 /* Process ID */
#ifdef CONFIG_BOOKE
#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
#endif
#endif

#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DSCR 0x11
@@ -527,7 +523,7 @@
#define SPRN_TSCR 0x399 /* Thread Switch Control Register */

#define SPRN_DEC 0x016 /* Decrement Register */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer (40x/BOOKE) */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer (BOOKE) */

#define SPRN_DER 0x095 /* Debug Enable Register */
#define DER_RSTE 0x40000000 /* Reset Interrupt */
@@ -1116,15 +1112,6 @@
* - SPRG2 indicator that we are in RTAS
* - SPRG4 (603 only) pseudo TLB LRU data
*
* 32-bit 40x:
* - SPRG0 scratch for exception vectors
* - SPRG1 scratch for exception vectors
* - SPRG2 scratch for exception vectors
* - SPRG4 scratch for exception vectors (not 403)
* - SPRG5 scratch for exception vectors (not 403)
* - SPRG6 scratch for exception vectors (not 403)
* - SPRG7 scratch for exception vectors (not 403)
*
* 32-bit 440 and FSL BookE:
* - SPRG0 scratch for exception vectors
* - SPRG1 scratch for exception vectors (*)
@@ -1216,16 +1203,6 @@
#define SPRN_SPRG_603_LRU SPRN_SPRG4
#endif

#ifdef CONFIG_40x
#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
#endif

#ifdef CONFIG_BOOKE
#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
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