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drm/amdgpu: drop temp programming for pagefault handling
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Was introduced as workaround. not needed anymore

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored and Alex Deucher committed Apr 13, 2023
1 parent ff742e0 commit 73c4b0f
Showing 1 changed file with 0 additions and 22 deletions.
22 changes: 0 additions & 22 deletions drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
Original file line number Diff line number Diff line change
@@ -417,34 +417,12 @@ static void gfxhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);
WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);

/**
* Set GRBM_GFX_INDEX in broad cast mode
* before programming GL1C_UTCL0_CNTL1 and SQG_CONFIG
*/
WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, regGRBM_GFX_INDEX_DEFAULT);

/**
* Retry respond mode: RETRY
* Error (no retry) respond mode: SUCCESS
*/
tmp = RREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1);
tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_MODE, 0);
tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_FAULT_MODE, 0x2);
WREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1, tmp);

/* These registers are not accessible to VF-SRIOV.
* The PF will program them instead.
*/
if (amdgpu_sriov_vf(adev))
return;

/* Disable SQ XNACK interrupt for all VMIDs */
tmp = RREG32_SOC15(GC, 0, regSQG_CONFIG);
tmp = REG_SET_FIELD(tmp, SQG_CONFIG, XNACK_INTR_MASK,
SQG_CONFIG__XNACK_INTR_MASK_MASK >>
SQG_CONFIG__XNACK_INTR_MASK__SHIFT);
WREG32_SOC15(GC, 0, regSQG_CONFIG, tmp);

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

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