Skip to content

Commit

Permalink
perf vendor events intel: Broadwellx v20 events
Browse files Browse the repository at this point in the history 
Updates descriptions and encodings. Adds BR_MISP_EXEC.INDIRECT events.

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Samantha Alt <samantha.alt@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
  • Loading branch information
Ian Rogers authored and Arnaldo Carvalho de Melo committed Apr 4, 2023
1 parent 8aae803 commit 74a87b6
Show file tree
Hide file tree
Showing 9 changed files with 403 additions and 469 deletions.
16 changes: 8 additions & 8 deletions tools/perf/pmu-events/arch/x86/broadwellx/cache.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,15 +8,15 @@
"UMask": "0x1"
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "L1D miss oustandings duration in cycles",
"BriefDescription": "L1D miss outstandings duration in cycles",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
Expand Down Expand Up @@ -454,22 +454,22 @@
"UMask": "0x20"
},
{
"BriefDescription": "All retired load uops.",
"BriefDescription": "Retired load uops.",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1",
"PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.",
"PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
"SampleAfterValue": "2000003",
"UMask": "0x81"
},
{
"BriefDescription": "All retired store uops.",
"BriefDescription": "Retired store uops.",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PEBS": "1",
"PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
"PublicDescription": "Counts all retired store uops.",
"SampleAfterValue": "2000003",
"UMask": "0x82"
},
Expand Down Expand Up @@ -541,10 +541,10 @@
"UMask": "0x80"
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests",
"BriefDescription": "Cacheable and non-cacheable code read requests",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
"PublicDescription": "This event counts both cacheable and non-cacheable code read requests.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
Expand Down
18 changes: 9 additions & 9 deletions tools/perf/pmu-events/arch/x86/broadwellx/frontend.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -125,16 +125,16 @@
"UMask": "0x4"
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
Expand All @@ -143,7 +143,7 @@
"UMask": "0x10"
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
Expand All @@ -153,18 +153,18 @@
"UMask": "0x10"
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
Expand All @@ -178,10 +178,10 @@
"UMask": "0x30"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
Expand Down
20 changes: 14 additions & 6 deletions tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -214,6 +214,14 @@
"SampleAfterValue": "200003",
"UMask": "0xc4"
},
{
"BriefDescription": "Speculative mispredicted indirect branches",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT",
"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).",
"SampleAfterValue": "200003",
"UMask": "0xe4"
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
"EventCode": "0x89",
Expand Down Expand Up @@ -500,7 +508,7 @@
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
"PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
Expand Down Expand Up @@ -909,7 +917,7 @@
},
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 0.",
"BriefDescription": "Cycles per core when uops are executed in port 0.",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003",
Expand All @@ -925,7 +933,7 @@
},
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 1.",
"BriefDescription": "Cycles per core when uops are executed in port 1.",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
Expand Down Expand Up @@ -973,7 +981,7 @@
},
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 4.",
"BriefDescription": "Cycles per core when uops are executed in port 4.",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
Expand All @@ -989,7 +997,7 @@
},
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 5.",
"BriefDescription": "Cycles per core when uops are executed in port 5.",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003",
Expand All @@ -1005,7 +1013,7 @@
},
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 6.",
"BriefDescription": "Cycles per core when uops are executed in port 6.",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
"SampleAfterValue": "2000003",
Expand Down
Loading

0 comments on commit 74a87b6

Please sign in to comment.