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ARM: dts: rockchip: add usb phys to Cortex-A9 socs
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This adds the usbphy nodes to rk3066 and rk3188, which share the usb hosts
in rk3xxx.dtsi and also enables it on boards based around these socs.

The usb-phy itself is the same as used on the rk3288 already.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Heiko Stuebner committed Aug 8, 2015
1 parent ec32bd9 commit 760bb97
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Showing 6 changed files with 60 additions and 0 deletions.
4 changes: 4 additions & 0 deletions arch/arm/boot/dts/rk3066a-marsboard.dts
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Expand Up @@ -202,6 +202,10 @@
status = "okay";
};

&usbphy {
status = "okay";
};

&wdt {
status = "okay";
};
4 changes: 4 additions & 0 deletions arch/arm/boot/dts/rk3066a-rayeager.dts
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Expand Up @@ -460,6 +460,10 @@
status = "okay";
};

&usbphy {
status = "okay";
};

&usb_otg {
status = "okay";
};
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22 changes: 22 additions & 0 deletions arch/arm/boot/dts/rk3066a.dtsi
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Expand Up @@ -169,6 +169,28 @@
clock-names = "timer", "pclk";
};

usbphy: phy {
compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";

usbphy0: usb-phy0 {
#phy-cells = <0>;
reg = <0x17c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
};

usbphy1: usb-phy1 {
#phy-cells = <0>;
reg = <0x188>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
};
};

pinctrl: pinctrl {
compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>;
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4 changes: 4 additions & 0 deletions arch/arm/boot/dts/rk3188-radxarock.dts
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Expand Up @@ -359,6 +359,10 @@
status = "okay";
};

&usbphy {
status = "okay";
};

&usb_host {
status = "okay";
};
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22 changes: 22 additions & 0 deletions arch/arm/boot/dts/rk3188.dtsi
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Expand Up @@ -130,6 +130,28 @@
#reset-cells = <1>;
};

usbphy: phy {
compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";

usbphy0: usb-phy0 {
#phy-cells = <0>;
reg = <0x10c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
};

usbphy1: usb-phy1 {
#phy-cells = <0>;
reg = <0x11c>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
};
};

pinctrl: pinctrl {
compatible = "rockchip,rk3188-pinctrl";
rockchip,grf = <&grf>;
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4 changes: 4 additions & 0 deletions arch/arm/boot/dts/rk3xxx.dtsi
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Expand Up @@ -177,6 +177,8 @@
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
g-use-dma;
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
};

Expand All @@ -187,6 +189,8 @@
clocks = <&cru HCLK_OTG1>;
clock-names = "otg";
dr_mode = "host";
phys = <&usbphy1>;
phy-names = "usb2-phy";
status = "disabled";
};

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