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drm/i915/guc: Update to GuC version 69.0.3
Update to the latest GuC release. The latest GuC firmware introduces a number of interface changes: GuC may return NO_RESPONSE_RETRY message for requests sent over CTB. Add support for this reply and try resending the request again as a new CTB message. A KLV (key-length-value) mechanism is now used for passing configuration data such as CTB management. With the new KLV scheme, the old CTB management actions are no longer used and are removed. Register capture on hang is now supported by GuC. Full i915 support for this will be added by a later patch. A minimum support of providing capture memory and register lists is required though, so add that in. The device id of the current platform needs to be provided at init time. The 'poll CS' w/a (Wa_22012773006) was blanket enabled by previous versions of GuC. It must now be explicitly requested by the KMD. So, add in the code to turn it on when relevant. The GuC log entry format has changed. This requires adding a new field to the log header structure to mark the wrap point at the end of the buffer (as the buffer size is no longer a multiple of the log entry size). New CTB notification messages are now sent for some things that were previously only sent via MMIO notifications. Of these, the crash dump notification was not really being handled by i915. It called the log flush code but that only flushed the regular debug log and then only if relay logging was enabled. So just report an error message instead. The 'exception' notification was just being ignored completely. So add an error message for that as well. Note that in either the crash dump or the exception case, the GuC is basically dead. The KMD will detect this via the heartbeat and trigger both an error log (which will include the crash dump as part of the GuC log) and a GT reset. So no other processing is really required. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220107000622.292081-3-John.C.Harrison@Intel.com
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| Original file line number | Diff line number | Diff line change |
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| /* SPDX-License-Identifier: MIT */ | ||
| /* | ||
| * Copyright © 2021 Intel Corporation | ||
| */ | ||
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| #ifndef _ABI_GUC_KLVS_ABI_H | ||
| #define _ABI_GUC_KLVS_ABI_H | ||
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| /** | ||
| * DOC: GuC KLV | ||
| * | ||
| * +---+-------+--------------------------------------------------------------+ | ||
| * | | Bits | Description | | ||
| * +===+=======+==============================================================+ | ||
| * | 0 | 31:16 | **KEY** - KLV key identifier | | ||
| * | | | - `GuC Self Config KLVs`_ | | ||
| * | | | | | ||
| * | +-------+--------------------------------------------------------------+ | ||
| * | | 15:0 | **LEN** - length of VALUE (in 32bit dwords) | | ||
| * +---+-------+--------------------------------------------------------------+ | ||
| * | 1 | 31:0 | **VALUE** - actual value of the KLV (format depends on KEY) | | ||
| * +---+-------+ | | ||
| * |...| | | | ||
| * +---+-------+ | | ||
| * | n | 31:0 | | | ||
| * +---+-------+--------------------------------------------------------------+ | ||
| */ | ||
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| #define GUC_KLV_LEN_MIN 1u | ||
| #define GUC_KLV_0_KEY (0xffff << 16) | ||
| #define GUC_KLV_0_LEN (0xffff << 0) | ||
| #define GUC_KLV_n_VALUE (0xffffffff << 0) | ||
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| /** | ||
| * DOC: GuC Self Config KLVs | ||
| * | ||
| * `GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_. | ||
| * | ||
| * _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR` : 0x0902 | ||
| * Refers to 64 bit Global Gfx address of H2G `CT Buffer`_. | ||
| * Should be above WOPCM address but below APIC base address for native mode. | ||
| * | ||
| * _`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR` : 0x0903 | ||
| * Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_. | ||
| * Should be above WOPCM address but below APIC base address for native mode. | ||
| * | ||
| * _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE` : 0x0904 | ||
| * Refers to size of H2G `CT Buffer`_ in bytes. | ||
| * Should be a multiple of 4K. | ||
| * | ||
| * _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR` : 0x0905 | ||
| * Refers to 64 bit Global Gfx address of G2H `CT Buffer`_. | ||
| * Should be above WOPCM address but below APIC base address for native mode. | ||
| * | ||
| * _`GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR` : 0x0906 | ||
| * Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_. | ||
| * Should be above WOPCM address but below APIC base address for native mode. | ||
| * | ||
| * _`GUC_KLV_SELF_CFG_G2H_CTB_SIZE` : 0x0907 | ||
| * Refers to size of G2H `CT Buffer`_ in bytes. | ||
| * Should be a multiple of 4K. | ||
| */ | ||
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| #define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_KEY 0x0902 | ||
| #define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_LEN 2u | ||
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| #define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_KEY 0x0903 | ||
| #define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_LEN 2u | ||
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| #define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_KEY 0x0904 | ||
| #define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_LEN 1u | ||
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| #define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_KEY 0x0905 | ||
| #define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_LEN 2u | ||
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| #define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_KEY 0x0906 | ||
| #define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_LEN 2u | ||
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| #define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_KEY 0x0907 | ||
| #define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_LEN 1u | ||
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| #endif /* _ABI_GUC_KLVS_ABI_H */ |
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