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octeontx2-af: NPA block admin queue init
Initialize NPA admin queue (AQ) i.e alloc memory for AQ instructions and for the results. All NPA LFs will submit instructions to AQ to init/write/read Aura/Pool contexts and in case of read, get context from result memory. Added some common APIs for allocating memory for a queue and get IOVA in return, these APIs will be used by NIX AQ and for other purposes. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Sunil Goutham
authored and
David S. Miller
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Oct 18, 2018
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,99 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0 | ||
| * Marvell OcteonTx2 RVU Admin Function driver | ||
| * | ||
| * Copyright (C) 2018 Marvell International Ltd. | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
|
|
||
| #ifndef COMMON_H | ||
| #define COMMON_H | ||
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| #include "rvu_struct.h" | ||
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| #define OTX2_ALIGN 128 /* Align to cacheline */ | ||
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| #define Q_SIZE_16 0ULL /* 16 entries */ | ||
| #define Q_SIZE_64 1ULL /* 64 entries */ | ||
| #define Q_SIZE_256 2ULL | ||
| #define Q_SIZE_1K 3ULL | ||
| #define Q_SIZE_4K 4ULL | ||
| #define Q_SIZE_16K 5ULL | ||
| #define Q_SIZE_64K 6ULL | ||
| #define Q_SIZE_256K 7ULL | ||
| #define Q_SIZE_1M 8ULL /* Million entries */ | ||
| #define Q_SIZE_MIN Q_SIZE_16 | ||
| #define Q_SIZE_MAX Q_SIZE_1M | ||
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| #define Q_COUNT(x) (16ULL << (2 * x)) | ||
| #define Q_SIZE(x, n) ((ilog2(x) - (n)) / 2) | ||
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| /* Admin queue info */ | ||
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| /* Since we intend to add only one instruction at a time, | ||
| * keep queue size to it's minimum. | ||
| */ | ||
| #define AQ_SIZE Q_SIZE_16 | ||
| /* HW head & tail pointer mask */ | ||
| #define AQ_PTR_MASK 0xFFFFF | ||
|
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| struct qmem { | ||
| void *base; | ||
| dma_addr_t iova; | ||
| int alloc_sz; | ||
| u8 entry_sz; | ||
| u8 align; | ||
| u32 qsize; | ||
| }; | ||
|
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| static inline int qmem_alloc(struct device *dev, struct qmem **q, | ||
| int qsize, int entry_sz) | ||
| { | ||
| struct qmem *qmem; | ||
| int aligned_addr; | ||
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| if (!qsize) | ||
| return -EINVAL; | ||
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| *q = devm_kzalloc(dev, sizeof(*qmem), GFP_KERNEL); | ||
| if (!*q) | ||
| return -ENOMEM; | ||
| qmem = *q; | ||
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| qmem->entry_sz = entry_sz; | ||
| qmem->alloc_sz = (qsize * entry_sz) + OTX2_ALIGN; | ||
| qmem->base = dma_zalloc_coherent(dev, qmem->alloc_sz, | ||
| &qmem->iova, GFP_KERNEL); | ||
| if (!qmem->base) | ||
| return -ENOMEM; | ||
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| qmem->qsize = qsize; | ||
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| aligned_addr = ALIGN((u64)qmem->iova, OTX2_ALIGN); | ||
| qmem->align = (aligned_addr - qmem->iova); | ||
| qmem->base += qmem->align; | ||
| qmem->iova += qmem->align; | ||
| return 0; | ||
| } | ||
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| static inline void qmem_free(struct device *dev, struct qmem *qmem) | ||
| { | ||
| if (!qmem) | ||
| return; | ||
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| if (qmem->base) | ||
| dma_free_coherent(dev, qmem->alloc_sz, | ||
| qmem->base - qmem->align, | ||
| qmem->iova - qmem->align); | ||
| devm_kfree(dev, qmem); | ||
| } | ||
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| struct admin_queue { | ||
| struct qmem *inst; | ||
| struct qmem *res; | ||
| spinlock_t lock; /* Serialize inst enqueue from PFs */ | ||
| }; | ||
|
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||
| #endif /* COMMON_H */ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,86 @@ | ||
| // SPDX-License-Identifier: GPL-2.0 | ||
| /* Marvell OcteonTx2 RVU Admin Function driver | ||
| * | ||
| * Copyright (C) 2018 Marvell International Ltd. | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
|
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| #include <linux/module.h> | ||
| #include <linux/pci.h> | ||
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| #include "rvu_struct.h" | ||
| #include "rvu_reg.h" | ||
| #include "rvu.h" | ||
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| static int npa_aq_init(struct rvu *rvu, struct rvu_block *block) | ||
| { | ||
| u64 cfg; | ||
| int err; | ||
|
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| /* Set admin queue endianness */ | ||
| cfg = rvu_read64(rvu, block->addr, NPA_AF_GEN_CFG); | ||
| #ifdef __BIG_ENDIAN | ||
| cfg |= BIT_ULL(1); | ||
| rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg); | ||
| #else | ||
| cfg &= ~BIT_ULL(1); | ||
| rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg); | ||
| #endif | ||
|
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| /* Do not bypass NDC cache */ | ||
| cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG); | ||
| cfg &= ~0x03DULL; | ||
| rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg); | ||
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| /* Result structure can be followed by Aura/Pool context at | ||
| * RES + 128bytes and a write mask at RES + 256 bytes, depending on | ||
| * operation type. Alloc sufficient result memory for all operations. | ||
| */ | ||
| err = rvu_aq_alloc(rvu, &block->aq, | ||
| Q_COUNT(AQ_SIZE), sizeof(struct npa_aq_inst_s), | ||
| ALIGN(sizeof(struct npa_aq_res_s), 128) + 256); | ||
| if (err) | ||
| return err; | ||
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| rvu_write64(rvu, block->addr, NPA_AF_AQ_CFG, AQ_SIZE); | ||
| rvu_write64(rvu, block->addr, | ||
| NPA_AF_AQ_BASE, (u64)block->aq->inst->iova); | ||
| return 0; | ||
| } | ||
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| int rvu_npa_init(struct rvu *rvu) | ||
| { | ||
| struct rvu_hwinfo *hw = rvu->hw; | ||
| struct rvu_block *block; | ||
| int blkaddr, err; | ||
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| blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); | ||
| if (blkaddr < 0) | ||
| return 0; | ||
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| block = &hw->block[blkaddr]; | ||
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| /* Initialize admin queue */ | ||
| err = npa_aq_init(rvu, &hw->block[blkaddr]); | ||
| if (err) | ||
| return err; | ||
|
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| return 0; | ||
| } | ||
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| void rvu_npa_freemem(struct rvu *rvu) | ||
| { | ||
| struct rvu_hwinfo *hw = rvu->hw; | ||
| struct rvu_block *block; | ||
| int blkaddr, err; | ||
|
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| blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); | ||
| if (blkaddr < 0) | ||
| return; | ||
|
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| block = &hw->block[blkaddr]; | ||
| rvu_aq_free(rvu, &block->aq); | ||
| } |
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