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MIPS: JZ4780: CI20: DTS: add SPI controller config
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1. Add nodes for the two SPI controllers found in MIPS Creator CI20.
2. Reparent SPI clock source to effectively use MPLL and set its clock
   rate to 54MHz.

NOTE: To use the SPI controllers, `pinctrl-0` property must be set in
order to configure the used pins. As SPI functionality is multiplexed on
multiple pin groups, this choice is left to the user.

An example configuration:
```
 &spi0 {
         pinctrl-0 = <&pins_spi0>;
 }

 pins_spi0: spi0 {
         function = "ssi0";
         groups = "ssi0-dt-e", "ssi0-dr-e", "ssi0-clk-e",
                  "ssi0-ce0-e", "ssi0-ce1-e";
         bias-disable;
 };
```
Consult the CI20 pinout description for more details.

Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Link: https://lore.kernel.org/r/20210830230139.21476-4-contact@artur-rojek.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
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Artur Rojek authored and Mark Brown committed Sep 13, 2021
1 parent ae5f94c commit 7b3fd81
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Showing 2 changed files with 38 additions and 15 deletions.
9 changes: 6 additions & 3 deletions arch/mips/boot/dts/ingenic/ci20.dts
Original file line number Diff line number Diff line change
Expand Up @@ -113,9 +113,12 @@
* Use the 32.768 kHz oscillator as the parent of the RTC for a higher
* precision.
*/
assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>;
assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
assigned-clock-rates = <48000000>;
assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
<&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>;
assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
<&cgu JZ4780_CLK_MPLL>,
<&cgu JZ4780_CLK_SSIPLL>;
assigned-clock-rates = <48000000>, <0>, <54000000>;
};

&tcu {
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44 changes: 32 additions & 12 deletions arch/mips/boot/dts/ingenic/jz4780.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -255,22 +255,23 @@
};
};

spi_gpio {
compatible = "spi-gpio";
spi0: spi@10043000 {
compatible = "ingenic,jz4780-spi";
reg = <0x10043000 0x1c>;
#address-cells = <1>;
#size-cells = <0>;
num-chipselects = <2>;

gpio-miso = <&gpe 14 0>;
gpio-sck = <&gpe 15 0>;
gpio-mosi = <&gpe 17 0>;
cs-gpios = <&gpe 16 0>, <&gpe 18 0>;
interrupt-parent = <&intc>;
interrupts = <8>;

spidev@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <1000000>;
};
clocks = <&cgu JZ4780_CLK_SSI0>;
clock-names = "spi";

dmas = <&dma JZ4780_DMA_SSI0_RX 0xffffffff>,
<&dma JZ4780_DMA_SSI0_TX 0xffffffff>;
dma-names = "rx", "tx";

status = "disabled";
};

uart0: serial@10030000 {
Expand Down Expand Up @@ -338,6 +339,25 @@
status = "disabled";
};

spi1: spi@10044000 {
compatible = "ingenic,jz4780-spi";
reg = <0x10044000 0x1c>;
#address-cells = <1>;
#size-sells = <0>;

interrupt-parent = <&intc>;
interrupts = <7>;

clocks = <&cgu JZ4780_CLK_SSI1>;
clock-names = "spi";

dmas = <&dma JZ4780_DMA_SSI1_RX 0xffffffff>,
<&dma JZ4780_DMA_SSI1_TX 0xffffffff>;
dma-names = "rx", "tx";

status = "disabled";
};

i2c0: i2c@10050000 {
compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
#address-cells = <1>;
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