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drm/amd/pm: drop unnecessary wrappers around watermark setting
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The convertion to "struct dm_pp_clock_range_for_mcif_wm_set_soc15"
is totally unnecessary and can be dropped.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Changfeng Zhu <Changfeng.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored and Alex Deucher committed Sep 17, 2020
1 parent 12684c6 commit 7b9c7e3
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Showing 6 changed files with 78 additions and 206 deletions.
97 changes: 2 additions & 95 deletions drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -664,49 +664,8 @@ static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
{
const struct dc_context *ctx = pp->dm;
struct amdgpu_device *adev = ctx->driver_context;
struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
wm_with_clock_ranges.wm_dmif_clocks_ranges;
struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =
wm_with_clock_ranges.wm_mcif_clocks_ranges;
int32_t i;

wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;

for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
if (ranges->reader_wm_sets[i].wm_inst > 3)
wm_dce_clocks[i].wm_set_id = WM_SET_A;
else
wm_dce_clocks[i].wm_set_id =
ranges->reader_wm_sets[i].wm_inst;
wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000;
wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000;
wm_dce_clocks[i].wm_max_mem_clk_in_khz =
ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000;
wm_dce_clocks[i].wm_min_mem_clk_in_khz =
ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000;
}

for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
if (ranges->writer_wm_sets[i].wm_inst > 3)
wm_soc_clocks[i].wm_set_id = WM_SET_A;
else
wm_soc_clocks[i].wm_set_id =
ranges->writer_wm_sets[i].wm_inst;
wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000;
wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000;
wm_soc_clocks[i].wm_max_mem_clk_in_khz =
ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000;
wm_soc_clocks[i].wm_min_mem_clk_in_khz =
ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
}

smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
smu_set_watermarks_for_clock_ranges(&adev->smu, ranges);

return PP_SMU_RESULT_OK;
}
Expand Down Expand Up @@ -917,60 +876,8 @@ static enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
{
const struct dc_context *ctx = pp->dm;
struct amdgpu_device *adev = ctx->driver_context;
struct smu_context *smu = &adev->smu;
struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
wm_with_clock_ranges.wm_dmif_clocks_ranges;
struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =
wm_with_clock_ranges.wm_mcif_clocks_ranges;
int32_t i;

if (!smu->ppt_funcs)
return PP_SMU_RESULT_UNSUPPORTED;

wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;

for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
if (ranges->reader_wm_sets[i].wm_inst > 3)
wm_dce_clocks[i].wm_set_id = WM_SET_A;
else
wm_dce_clocks[i].wm_set_id =
ranges->reader_wm_sets[i].wm_inst;

wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
ranges->reader_wm_sets[i].min_drain_clk_mhz;

wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
ranges->reader_wm_sets[i].max_drain_clk_mhz;

wm_dce_clocks[i].wm_min_mem_clk_in_khz =
ranges->reader_wm_sets[i].min_fill_clk_mhz;

wm_dce_clocks[i].wm_max_mem_clk_in_khz =
ranges->reader_wm_sets[i].max_fill_clk_mhz;
}

for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
if (ranges->writer_wm_sets[i].wm_inst > 3)
wm_soc_clocks[i].wm_set_id = WM_SET_A;
else
wm_soc_clocks[i].wm_set_id =
ranges->writer_wm_sets[i].wm_inst;
wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
ranges->writer_wm_sets[i].min_fill_clk_mhz;

wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
ranges->writer_wm_sets[i].max_fill_clk_mhz;

wm_soc_clocks[i].wm_min_mem_clk_in_khz =
ranges->writer_wm_sets[i].min_drain_clk_mhz;

wm_soc_clocks[i].wm_max_mem_clk_in_khz =
ranges->writer_wm_sets[i].max_drain_clk_mhz;
}

smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
smu_set_watermarks_for_clock_ranges(&adev->smu, ranges);

return PP_SMU_RESULT_OK;
}
Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -501,7 +501,7 @@ struct pptable_funcs {
bool (*is_dpm_running)(struct smu_context *smu);
int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
int (*set_watermarks_table)(struct smu_context *smu,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
struct pp_smu_wm_range_sets *clock_ranges);
int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
int (*set_default_od_settings)(struct smu_context *smu);
Expand Down Expand Up @@ -755,7 +755,7 @@ enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
int smu_write_watermarks_table(struct smu_context *smu);
int smu_set_watermarks_for_clock_ranges(
struct smu_context *smu,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
struct pp_smu_wm_range_sets *clock_ranges);

/* smu to display interface */
extern int smu_display_configuration_change(struct smu_context *smu, const
Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1828,7 +1828,7 @@ int smu_write_watermarks_table(struct smu_context *smu)
}

int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
struct pp_smu_wm_range_sets *clock_ranges)
{
int ret = 0;

Expand Down
68 changes: 27 additions & 41 deletions drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1589,57 +1589,43 @@ static int navi10_notify_smc_display_config(struct smu_context *smu)
}

static int navi10_set_watermarks_table(struct smu_context *smu,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
struct pp_smu_wm_range_sets *clock_ranges)
{
Watermarks_t *table = smu->smu_table.watermarks_table;
int ret = 0;
int i;

if (clock_ranges) {
if (clock_ranges->num_wm_dmif_sets > 4 ||
clock_ranges->num_wm_mcif_sets > 4)
if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
return -EINVAL;

for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
table->WatermarkRow[1][i].MinClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1000));
table->WatermarkRow[1][i].MaxClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1000));
table->WatermarkRow[1][i].MinUclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1000));
table->WatermarkRow[1][i].MaxUclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1000));
table->WatermarkRow[1][i].WmSetting = (uint8_t)
clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
table->WatermarkRow[WM_DCEFCLK][i].MinClock =
clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;

table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
clock_ranges->reader_wm_sets[i].wm_inst;
}

for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
table->WatermarkRow[0][i].MinClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1000));
table->WatermarkRow[0][i].MaxClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1000));
table->WatermarkRow[0][i].MinUclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1000));
table->WatermarkRow[0][i].MaxUclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1000));
table->WatermarkRow[0][i].WmSetting = (uint8_t)
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
table->WatermarkRow[WM_SOCCLK][i].MinClock =
clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MaxClock =
clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MinUclk =
clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;

table->WatermarkRow[WM_SOCCLK][i].WmSetting =
clock_ranges->writer_wm_sets[i].wm_inst;
}

smu->watermarks_bitmap |= WATERMARKS_EXIST;
Expand Down
69 changes: 27 additions & 42 deletions drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1407,58 +1407,43 @@ static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
}

static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
struct dm_pp_wm_sets_with_clock_ranges_soc15
*clock_ranges)
struct pp_smu_wm_range_sets *clock_ranges)
{
Watermarks_t *table = smu->smu_table.watermarks_table;
int ret = 0;
int i;

if (clock_ranges) {
if (clock_ranges->num_wm_dmif_sets > 4 ||
clock_ranges->num_wm_mcif_sets > 4)
if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
return -EINVAL;

for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
table->WatermarkRow[1][i].MinClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1000));
table->WatermarkRow[1][i].MaxClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1000));
table->WatermarkRow[1][i].MinUclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1000));
table->WatermarkRow[1][i].MaxUclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1000));
table->WatermarkRow[1][i].WmSetting = (uint8_t)
clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
table->WatermarkRow[WM_DCEFCLK][i].MinClock =
clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;

table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
clock_ranges->reader_wm_sets[i].wm_inst;
}

for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
table->WatermarkRow[0][i].MinClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1000));
table->WatermarkRow[0][i].MaxClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1000));
table->WatermarkRow[0][i].MinUclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1000));
table->WatermarkRow[0][i].MaxUclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1000));
table->WatermarkRow[0][i].WmSetting = (uint8_t)
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
table->WatermarkRow[WM_SOCCLK][i].MinClock =
clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MaxClock =
clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MinUclk =
clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;

table->WatermarkRow[WM_SOCCLK][i].WmSetting =
clock_ranges->writer_wm_sets[i].wm_inst;
}

smu->watermarks_bitmap |= WATERMARKS_EXIST;
Expand Down
44 changes: 19 additions & 25 deletions drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -863,50 +863,44 @@ static int renoir_set_performance_level(struct smu_context *smu,
*/
static int renoir_set_watermarks_table(
struct smu_context *smu,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
struct pp_smu_wm_range_sets *clock_ranges)
{
Watermarks_t *table = smu->smu_table.watermarks_table;
int ret = 0;
int i;

if (clock_ranges) {
if (clock_ranges->num_wm_dmif_sets > 4 ||
clock_ranges->num_wm_mcif_sets > 4)
if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
return -EINVAL;

/* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
table->WatermarkRow[WM_DCFCLK][i].MinClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
table->WatermarkRow[WM_DCFCLK][i].MaxClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
table->WatermarkRow[WM_DCFCLK][i].MinMclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;

table->WatermarkRow[WM_DCFCLK][i].WmSetting =
clock_ranges->reader_wm_sets[i].wm_inst;
}

for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
table->WatermarkRow[WM_SOCCLK][i].MinClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MaxClock =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MinMclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
cpu_to_le16((uint16_t)
(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;

table->WatermarkRow[WM_SOCCLK][i].WmSetting =
clock_ranges->writer_wm_sets[i].wm_inst;
}

smu->watermarks_bitmap |= WATERMARKS_EXIST;
Expand Down

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