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onfiguration'

Geert Uytterhoeven says:

====================
net/ravb: Add support for explicit internal clock delay configuration

Some Renesas EtherAVB variants support internal clock delay
configuration, which can add larger delays than the delays that are
typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or
"[rt]xc-skew-ps" properties).

Historically, the EtherAVB driver configured these delays based on the
"rgmii-*id" PHY mode.  This caused issues with PHY drivers that
implement PHY internal delays properly[1].  Hence a backwards-compatible
workaround was added by masking the PHY mode[2].

This patch series implements the next step of the plan outlined in [3],
and adds proper support for explicit configuration of the MAC internal
clock delays using new "[rt]x-internal-delay-ps" properties.  If none of
these properties is present, the driver falls back to the old handling.

This can be considered the MAC counterpart of commit 9150069
("dt-bindings: net: Add tx and rx internal delays"), which applies to
the PHY.  Note that unlike commit 92252ee ("net: phy: Add a
helper to return the index for of the internal delay"), no helpers are
provided to parse the DT properties, as so far there is a single user
only, which supports only zero or a single fixed value.  Of course such
helpers can be added later, when the need arises, or when deemed useful
otherwise.

This series consists of 3 parts:
  1. DT binding updates documenting the new properties, for both the
     generic ethernet-controller and the EtherAVB-specific bindings,
  2. Conversion to json-schema of the Renesas EtherAVB DT bindings.
     Technically, the conversion is independent of all of the above.
     I included it in this series, as it shows how all sanity checks on
     "[rt]x-internal-delay-ps" values are implemented as DT binding
     checks,
  3. EtherAVB driver update implementing support for the new properties.

Given Rob has provided his acks for the DT binding updates, all of this
can be merged through net-next.

Changes compared to v3[4]:
  - Add Reviewed-by,
  - Drop the DT updates, as they will be merged through renesas-devel and
    arm-soc, and have a hard dependency on this series.

Changes compared to v2[5]:
  - Update recently added board DTS files,
  - Add Reviewed-by.

Changes compared to v1[6]:
  - Added "[PATCH 1/7] dt-bindings: net: ethernet-controller: Add
    internal delay properties",
  - Replace "renesas,[rt]xc-delay-ps" by "[rt]x-internal-delay-ps",
  - Incorporated EtherAVB DT binding conversion to json-schema,
  - Add Reviewed-by.

Impacted, tested:
  - Salvator-X(S) with R-Car H3 ES1.0 and ES2.0, M3-W, and M3-N.

Not impacted, tested:
  - Ebisu with R-Car E3.

Impacted, not tested:
  - Salvator-X(S) with other SoC variants,
  - ULCB with R-Car H3/M3-W/M3-N variants,
  - V3MSK and Eagle with R-Car V3M,
  - Draak with R-Car V3H,
  - HiHope RZ/G2[MN] with RZ/G2M or RZ/G2N,
  - Beacon EmbeddedWorks RZ/G2M Development Kit.

To ease testing, I have pushed this series and the DT updates to the
topic/ravb-internal-clock-delays-v4 branch of my renesas-drivers
repository at
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git.

Thanks for applying!

References:
  [1] Commit bcf3440 ("net: phy: micrel: add phy-mode support
      for the KSZ9031 PHY")
  [2] Commit 9b23203 ("ravb: Mask PHY mode to avoid inserting
      delays twice").
      https://lore.kernel.org/r/20200529122540.31368-1-geert+renesas@glider.be/
  [3] https://lore.kernel.org/r/CAMuHMdU+MR-2tr3-pH55G0GqPG9HwH3XUd=8HZxprFDMGQeWUw@mail.gmail.com/
  [4] https://lore.kernel.org/linux-devicetree/20200819134344.27813-1-geert+renesas@glider.be/
  [5] https://lore.kernel.org/linux-devicetree/20200706143529.18306-1-geert+renesas@glider.be/
  [6] https://lore.kernel.org/linux-devicetree/20200619191554.24942-1-geert+renesas@glider.be/
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
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14 changes: 14 additions & 0 deletions Documentation/devicetree/bindings/net/ethernet-controller.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -120,6 +120,13 @@ properties:
and is useful for determining certain configuration settings
such as flow control thresholds.

rx-internal-delay-ps:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RGMII Receive Clock Delay defined in pico seconds.
This is used for controllers that have configurable RX internal delays.
If this property is present then the MAC applies the RX delay.
sfp:
$ref: /schemas/types.yaml#definitions/phandle
description:
Expand All @@ -131,6 +138,13 @@ properties:
The size of the controller\'s transmit fifo in bytes. This
is used for components that can have configurable fifo sizes.

tx-internal-delay-ps:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RGMII Transmit Clock Delay defined in pico seconds.
This is used for controllers that have configurable TX internal delays.
If this property is present then the MAC applies the TX delay.
managed:
description:
Specifies the PHY management type. If auto is set and fixed-link
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261 changes: 261 additions & 0 deletions Documentation/devicetree/bindings/net/renesas,etheravb.yaml
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@@ -0,0 +1,261 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/renesas,etheravb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Ethernet AVB

maintainers:
- Sergei Shtylyov <sergei.shtylyov@gmail.com>

properties:
compatible:
oneOf:
- items:
- enum:
- renesas,etheravb-r8a7742 # RZ/G1H
- renesas,etheravb-r8a7743 # RZ/G1M
- renesas,etheravb-r8a7744 # RZ/G1N
- renesas,etheravb-r8a7745 # RZ/G1E
- renesas,etheravb-r8a77470 # RZ/G1C
- renesas,etheravb-r8a7790 # R-Car H2
- renesas,etheravb-r8a7791 # R-Car M2-W
- renesas,etheravb-r8a7792 # R-Car V2H
- renesas,etheravb-r8a7793 # R-Car M2-N
- renesas,etheravb-r8a7794 # R-Car E2
- const: renesas,etheravb-rcar-gen2 # R-Car Gen2 and RZ/G1

- items:
- enum:
- renesas,etheravb-r8a774a1 # RZ/G2M
- renesas,etheravb-r8a774b1 # RZ/G2N
- renesas,etheravb-r8a774c0 # RZ/G2E
- renesas,etheravb-r8a7795 # R-Car H3
- renesas,etheravb-r8a7796 # R-Car M3-W
- renesas,etheravb-r8a77961 # R-Car M3-W+
- renesas,etheravb-r8a77965 # R-Car M3-N
- renesas,etheravb-r8a77970 # R-Car V3M
- renesas,etheravb-r8a77980 # R-Car V3H
- renesas,etheravb-r8a77990 # R-Car E3
- renesas,etheravb-r8a77995 # R-Car D3
- const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2

reg: true

interrupts: true

interrupt-names: true

clocks:
maxItems: 1

iommus:
maxItems: 1

power-domains:
maxItems: 1

resets:
maxItems: 1

phy-mode: true

phy-handle: true

'#address-cells':
description: Number of address cells for the MDIO bus.
const: 1

'#size-cells':
description: Number of size cells on the MDIO bus.
const: 0

renesas,no-ether-link:
type: boolean
description:
Specify when a board does not provide a proper AVB_LINK signal.

renesas,ether-link-active-low:
type: boolean
description:
Specify when the AVB_LINK signal is active-low instead of normal
active-high.

rx-internal-delay-ps:
enum: [0, 1800]

tx-internal-delay-ps:
enum: [0, 2000]

patternProperties:
"^ethernet-phy@[0-9a-f]$":
type: object
$ref: ethernet-phy.yaml#

required:
- compatible
- reg
- interrupts
- clocks
- power-domains
- resets
- phy-mode
- phy-handle
- '#address-cells'
- '#size-cells'

allOf:
- $ref: ethernet-controller.yaml#

- if:
properties:
compatible:
contains:
enum:
- renesas,etheravb-rcar-gen2
- renesas,etheravb-r8a7795
- renesas,etheravb-r8a7796
- renesas,etheravb-r8a77961
- renesas,etheravb-r8a77965
then:
properties:
reg:
items:
- description: MAC register block
- description: Stream buffer
else:
properties:
reg:
items:
- description: MAC register block

- if:
properties:
compatible:
contains:
const: renesas,etheravb-rcar-gen2
then:
properties:
interrupts:
maxItems: 1
interrupt-names:
items:
- const: mux
rx-internal-delay-ps: false
else:
properties:
interrupts:
minItems: 25
maxItems: 25
interrupt-names:
items:
pattern: '^ch[0-9]+$'
required:
- interrupt-names
- rx-internal-delay-ps

- if:
properties:
compatible:
contains:
enum:
- renesas,etheravb-r8a774a1
- renesas,etheravb-r8a774b1
- renesas,etheravb-r8a7795
- renesas,etheravb-r8a7796
- renesas,etheravb-r8a77961
- renesas,etheravb-r8a77965
- renesas,etheravb-r8a77970
- renesas,etheravb-r8a77980
then:
required:
- tx-internal-delay-ps
else:
properties:
tx-internal-delay-ps: false

- if:
properties:
compatible:
contains:
const: renesas,etheravb-r8a77995
then:
properties:
rx-internal-delay-ps:
const: 1800

- if:
properties:
compatible:
contains:
const: renesas,etheravb-r8a77980
then:
properties:
tx-internal-delay-ps:
const: 2000

additionalProperties: false

examples:
- |
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7795-sysc.h>
#include <dt-bindings/gpio/gpio.h>
aliases {
ethernet0 = &avb;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7795",
"renesas,etheravb-rcar-gen3";
reg = <0xe6800000 0x800>, <0xe6a00000 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6",
"ch7", "ch8", "ch9", "ch10", "ch11", "ch12",
"ch13", "ch14", "ch15", "ch16", "ch17", "ch18",
"ch19", "ch20", "ch21", "ch22", "ch23", "ch24";
clocks = <&cpg CPG_MOD 812>;
iommus = <&ipmmu_ds0 16>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <2000>;
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
};
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