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dt-bindings: update risc-v cpu properties
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The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip
version using a draft verion of the RISC-V ISA specifications. To avoid
any confusion with CPU cores using stable specifications, add the
compatible string "canaan,k210" for this SoC CPU cores.

Also add the "riscv,none" value to the mmu-type property to allow a DT
to indicate that the CPU being described does not have an MMU or that
it has an MMU that is not usable (which is the case for the K210 SoC).

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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Damien Le Moal authored and Palmer Dabbelt committed Feb 23, 2021
1 parent 11481d6 commit 7ef71c7
Showing 1 changed file with 2 additions and 0 deletions.
2 changes: 2 additions & 0 deletions Documentation/devicetree/bindings/riscv/cpus.yaml
Original file line number Diff line number Diff line change
@@ -39,6 +39,7 @@ properties:
- sifive,u74
- sifive,u5
- sifive,u7
- canaan,k210
- const: riscv
- const: riscv # Simulator only
description:
@@ -56,6 +57,7 @@ properties:
- riscv,sv32
- riscv,sv39
- riscv,sv48
- riscv,none

riscv,isa:
description:

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