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RDMA/hns: Modify the data structure of hns_roce_av
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we change type of some members to u32/u8 from __le32 as well as
split sl_tclass_flowlabel into three variables in hns_roce_av.

Signed-off-by: Lang Cheng <chenglang@huawei.com>
Link: https://lore.kernel.org/r/1566393276-42555-4-git-send-email-oulijun@huawei.com
Signed-off-by: Doug Ledford <dledford@redhat.com>
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Lang Cheng authored and Doug Ledford committed Aug 28, 2019
1 parent a0d8994 commit 82e620d
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Showing 4 changed files with 18 additions and 31 deletions.
23 changes: 7 additions & 16 deletions drivers/infiniband/hw/hns/hns_roce_ah.c
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Original file line number Diff line number Diff line change
Expand Up @@ -66,11 +66,9 @@ int hns_roce_create_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr,
HNS_ROCE_VLAN_SL_SHIFT;
}

ah->av.port_pd = cpu_to_le32(to_hr_pd(ibah->pd)->pdn |
(rdma_ah_get_port_num(ah_attr) <<
HNS_ROCE_PORT_NUM_SHIFT));
ah->av.port = rdma_ah_get_port_num(ah_attr);
ah->av.gid_index = grh->sgid_index;
ah->av.vlan = cpu_to_le16(vlan_tag);
ah->av.vlan = vlan_tag;
ah->av.vlan_en = vlan_en;
dev_dbg(dev, "gid_index = 0x%x,vlan = 0x%x\n", ah->av.gid_index,
ah->av.vlan);
Expand All @@ -79,8 +77,7 @@ int hns_roce_create_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr,
ah->av.stat_rate = IB_RATE_10_GBPS;

memcpy(ah->av.dgid, grh->dgid.raw, HNS_ROCE_GID_SIZE);
ah->av.sl_tclass_flowlabel = cpu_to_le32(rdma_ah_get_sl(ah_attr) <<
HNS_ROCE_SL_SHIFT);
ah->av.sl = rdma_ah_get_sl(ah_attr);

return 0;
}
Expand All @@ -91,17 +88,11 @@ int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr)

memset(ah_attr, 0, sizeof(*ah_attr));

rdma_ah_set_sl(ah_attr, (le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
HNS_ROCE_SL_SHIFT));
rdma_ah_set_port_num(ah_attr, (le32_to_cpu(ah->av.port_pd) >>
HNS_ROCE_PORT_NUM_SHIFT));
rdma_ah_set_sl(ah_attr, ah->av.sl);
rdma_ah_set_port_num(ah_attr, ah->av.port);
rdma_ah_set_static_rate(ah_attr, ah->av.stat_rate);
rdma_ah_set_grh(ah_attr, NULL,
(le32_to_cpu(ah->av.sl_tclass_flowlabel) &
HNS_ROCE_FLOW_LABEL_MASK), ah->av.gid_index,
ah->av.hop_limit,
(le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
HNS_ROCE_TCLASS_SHIFT));
rdma_ah_set_grh(ah_attr, NULL, ah->av.flowlabel,
ah->av.gid_index, ah->av.hop_limit, ah->av.tclass);
rdma_ah_set_dgid_raw(ah_attr, ah->av.dgid);

return 0;
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8 changes: 5 additions & 3 deletions drivers/infiniband/hw/hns/hns_roce_device.h
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Original file line number Diff line number Diff line change
Expand Up @@ -568,14 +568,16 @@ struct hns_roce_raq_table {
};

struct hns_roce_av {
__le32 port_pd;
u8 port;
u8 gid_index;
u8 stat_rate;
u8 hop_limit;
__le32 sl_tclass_flowlabel;
u32 flowlabel;
u8 sl;
u8 tclass;
u8 dgid[HNS_ROCE_GID_SIZE];
u8 mac[ETH_ALEN];
__le16 vlan;
u16 vlan;
bool vlan_en;
};

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9 changes: 3 additions & 6 deletions drivers/infiniband/hw/hns/hns_roce_hw_v1.c
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Original file line number Diff line number Diff line change
Expand Up @@ -175,13 +175,11 @@ static int hns_roce_v1_post_send(struct ib_qp *ibqp,
roce_set_field(ud_sq_wqe->u32_36,
UD_SEND_WQE_U32_36_FLOW_LABEL_M,
UD_SEND_WQE_U32_36_FLOW_LABEL_S,
ah->av.sl_tclass_flowlabel &
HNS_ROCE_FLOW_LABEL_MASK);
ah->av.flowlabel);
roce_set_field(ud_sq_wqe->u32_36,
UD_SEND_WQE_U32_36_PRIORITY_M,
UD_SEND_WQE_U32_36_PRIORITY_S,
le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
HNS_ROCE_SL_SHIFT);
ah->av.sl);
roce_set_field(ud_sq_wqe->u32_36,
UD_SEND_WQE_U32_36_SGID_INDEX_M,
UD_SEND_WQE_U32_36_SGID_INDEX_S,
Expand All @@ -195,8 +193,7 @@ static int hns_roce_v1_post_send(struct ib_qp *ibqp,
roce_set_field(ud_sq_wqe->u32_40,
UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
ah->av.sl_tclass_flowlabel >>
HNS_ROCE_TCLASS_SHIFT);
ah->av.tclass);

memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);

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9 changes: 3 additions & 6 deletions drivers/infiniband/hw/hns/hns_roce_hw_v2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -397,18 +397,15 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp,
roce_set_field(ud_sq_wqe->byte_36,
V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
V2_UD_SEND_WQE_BYTE_36_TCLASS_S,
ah->av.sl_tclass_flowlabel >>
HNS_ROCE_TCLASS_SHIFT);
ah->av.tclass);
roce_set_field(ud_sq_wqe->byte_40,
V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S,
ah->av.sl_tclass_flowlabel &
HNS_ROCE_FLOW_LABEL_MASK);
ah->av.flowlabel);
roce_set_field(ud_sq_wqe->byte_40,
V2_UD_SEND_WQE_BYTE_40_SL_M,
V2_UD_SEND_WQE_BYTE_40_SL_S,
le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
HNS_ROCE_SL_SHIFT);
ah->av.sl);
roce_set_field(ud_sq_wqe->byte_40,
V2_UD_SEND_WQE_BYTE_40_PORTN_M,
V2_UD_SEND_WQE_BYTE_40_PORTN_S,
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