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intel_rapl: remove hardcoded register index
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enum rapl_domain_reg_id is defined for the RAPL registers for each RAPL
domain, thus use it whenever possible.

Reviewed-by: Pandruvada, Srinivas <srinivas.pandruvada@intel.com>
Tested-by: Pandruvada, Srinivas <srinivas.pandruvada@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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Zhang Rui authored and Rafael J. Wysocki committed Jul 11, 2019
1 parent f7c4e0c commit 8310e82
Showing 1 changed file with 22 additions and 22 deletions.
44 changes: 22 additions & 22 deletions drivers/powercap/intel_rapl.c
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Original file line number Diff line number Diff line change
Expand Up @@ -642,11 +642,11 @@ static void rapl_init_domains(struct rapl_package *rp)
case BIT(RAPL_DOMAIN_PACKAGE):
rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
rd->id = RAPL_DOMAIN_PACKAGE;
rd->regs[0] = MSR_PKG_POWER_LIMIT;
rd->regs[1] = MSR_PKG_ENERGY_STATUS;
rd->regs[2] = MSR_PKG_PERF_STATUS;
rd->regs[3] = 0;
rd->regs[4] = MSR_PKG_POWER_INFO;
rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PKG_POWER_LIMIT;
rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PKG_ENERGY_STATUS;
rd->regs[RAPL_DOMAIN_REG_PERF] = MSR_PKG_PERF_STATUS;
rd->regs[RAPL_DOMAIN_REG_POLICY] = 0;
rd->regs[RAPL_DOMAIN_REG_INFO] = MSR_PKG_POWER_INFO;
rd->rpl[0].prim_id = PL1_ENABLE;
rd->rpl[0].name = pl1_name;
rd->rpl[1].prim_id = PL2_ENABLE;
Expand All @@ -655,33 +655,33 @@ static void rapl_init_domains(struct rapl_package *rp)
case BIT(RAPL_DOMAIN_PP0):
rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
rd->id = RAPL_DOMAIN_PP0;
rd->regs[0] = MSR_PP0_POWER_LIMIT;
rd->regs[1] = MSR_PP0_ENERGY_STATUS;
rd->regs[2] = 0;
rd->regs[3] = MSR_PP0_POLICY;
rd->regs[4] = 0;
rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PP0_POWER_LIMIT;
rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PP0_ENERGY_STATUS;
rd->regs[RAPL_DOMAIN_REG_PERF] = 0;
rd->regs[RAPL_DOMAIN_REG_POLICY] = MSR_PP0_POLICY;
rd->regs[RAPL_DOMAIN_REG_INFO] = 0;
rd->rpl[0].prim_id = PL1_ENABLE;
rd->rpl[0].name = pl1_name;
break;
case BIT(RAPL_DOMAIN_PP1):
rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
rd->id = RAPL_DOMAIN_PP1;
rd->regs[0] = MSR_PP1_POWER_LIMIT;
rd->regs[1] = MSR_PP1_ENERGY_STATUS;
rd->regs[2] = 0;
rd->regs[3] = MSR_PP1_POLICY;
rd->regs[4] = 0;
rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PP1_POWER_LIMIT;
rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PP1_ENERGY_STATUS;
rd->regs[RAPL_DOMAIN_REG_PERF] = 0;
rd->regs[RAPL_DOMAIN_REG_POLICY] = MSR_PP1_POLICY;
rd->regs[RAPL_DOMAIN_REG_INFO] = 0;
rd->rpl[0].prim_id = PL1_ENABLE;
rd->rpl[0].name = pl1_name;
break;
case BIT(RAPL_DOMAIN_DRAM):
rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
rd->id = RAPL_DOMAIN_DRAM;
rd->regs[0] = MSR_DRAM_POWER_LIMIT;
rd->regs[1] = MSR_DRAM_ENERGY_STATUS;
rd->regs[2] = MSR_DRAM_PERF_STATUS;
rd->regs[3] = 0;
rd->regs[4] = MSR_DRAM_POWER_INFO;
rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_DRAM_POWER_LIMIT;
rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_DRAM_ENERGY_STATUS;
rd->regs[RAPL_DOMAIN_REG_PERF] = MSR_DRAM_PERF_STATUS;
rd->regs[RAPL_DOMAIN_REG_POLICY] = 0;
rd->regs[RAPL_DOMAIN_REG_INFO] = MSR_DRAM_POWER_INFO;
rd->rpl[0].prim_id = PL1_ENABLE;
rd->rpl[0].name = pl1_name;
rd->domain_energy_unit =
Expand Down Expand Up @@ -1282,8 +1282,8 @@ static int __init rapl_register_psys(void)

rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
rd->id = RAPL_DOMAIN_PLATFORM;
rd->regs[0] = MSR_PLATFORM_POWER_LIMIT;
rd->regs[1] = MSR_PLATFORM_ENERGY_STATUS;
rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PLATFORM_POWER_LIMIT;
rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PLATFORM_ENERGY_STATUS;
rd->rpl[0].prim_id = PL1_ENABLE;
rd->rpl[0].name = pl1_name;
rd->rpl[1].prim_id = PL2_ENABLE;
Expand Down

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