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Revert "CHROMIUM: ARM64: dts: Add sor & dpaux nodes to dts"
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This reverts commit 70710999123035298eac589b397a20dc22ac8a58.

DisplayPort isn't reliable enough to ship, disable it.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Change-Id: I93404349646e6bf136f1e4e5817fb1ec23018e01
Reviewed-on: https://chromium-review.googlesource.com/342614
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
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Sean Paul authored and Andrew Bresticker committed May 9, 2016
1 parent 161314b commit 8684b92
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Showing 2 changed files with 0 additions and 96 deletions.
24 changes: 0 additions & 24 deletions arch/arm64/boot/dts/tegra/tegra210-smaug.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -31,12 +31,6 @@
avdd-dsi-csi-supply = <&pp1200_avdd>;
};

dpaux@0,54040000 {
status = "okay";

vdd-supply = <&pp3300>;
};

dsia: dsi@54300000 {
status = "okay";
avdd-dsi-csi-supply = <&pp1200_avdd>;
Expand Down Expand Up @@ -72,24 +66,6 @@
touch = <&touchscreen>;
};
};

sor@0,54580000 {
status = "okay";

nvidia,dpaux = <&dpaux1>;

avdd-io-hdmi-dp-supply = <&pp1800>;
vdd-hdmi-dp-pll-supply = <&avddio_1v05>;
vddio-dp-supply = <&pp1800>;
vdd18-dp-supply = <&pp1800>;
nvidia,head = <1>;
};

/*
dpaux@0,545c0000 {
status = "okay";
};
*/
};

gpu@57000000 {
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72 changes: 0 additions & 72 deletions arch/arm64/boot/dts/tegra/tegra210.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -73,18 +73,6 @@
iommus = <&mc TEGRA_SWGROUP_VI>;
};

dpaux1: dpaux@0,54040000 {
compatible = "nvidia,tegra210-dpaux";
reg = <0x0 0x54040000 0x0 0x00040000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
<&tegra_car TEGRA210_CLK_PLL_DP>;
clock-names = "dpaux", "parent";
resets = <&tegra_car 207>;
reset-names = "dpaux";
status = "disabled";
};

dc@54200000 {
compatible = "nvidia,tegra210-dc";
reg = <0x0 0x54200000 0x0 0x00040000>;
Expand All @@ -105,26 +93,6 @@
nvidia,head = <0>;
};

dc@54240000 {
compatible = "nvidia,tegra210-dc";
reg = <0x0 0x54240000 0x0 0x00040000>;
reg-names = "dc";
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
//power-domains = <&pmc TEGRA_POWERGATE_DISB>;
clocks = <&tegra_car TEGRA210_CLK_DISP2>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_DISP2_EMC>,
<&tegra_car TEGRA210_CLK_DISP2_LA_EMC>;
clock-names = "dc", "parent", "emc", "emc_la";
resets = <&tegra_car TEGRA210_CLK_DISP2>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DCB>;
mc-clients = <&mc TEGRA_CLIENT_DISPLAY0AB>,
<&mc TEGRA_CLIENT_DISPLAY0BB>,
<&mc TEGRA_CLIENT_DISPLAY0CB>;
nvidia,head = <1>;
};

dsi@54300000 {
compatible = "nvidia,tegra210-dsi";
reg = <0x0 0x54300000 0x0 0x00040000>;
Expand Down Expand Up @@ -228,46 +196,6 @@
reset-names = "isp";
iommus = <&mc TEGRA_SWGROUP_ISP2B>;
};

sor@0,54540000 {
compatible = "nvidia,tegra210-sor";
reg = <0x0 0x54540000 0x0 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_DP>,
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
clock-names = "sor", "parent", "dp", "safe";
resets = <&tegra_car 182>;
reset-names = "sor";
status = "disabled";
};

sor@0,54580000 {
compatible = "nvidia,tegra210-sor1";
reg = <0x0 0x54580000 0x0 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SOR1>,
<&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_DP>,
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
clock-names = "sor", "parent", "dp", "safe";
resets = <&tegra_car 183>;
reset-names = "sor";
status = "disabled";
};

dpaux: dpaux@0,545c0000 {
compatible = "nvidia,tegra124-dpaux";
reg = <0x0 0x545c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
<&tegra_car TEGRA210_CLK_PLL_DP>;
clock-names = "dpaux", "parent";
resets = <&tegra_car 181>;
reset-names = "dpaux";
status = "disabled";
};
};

gpu@57000000 {
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