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Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
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* Renesas VMSA-Compatible IOMMU | ||
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The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables. | ||
It provides address translation for bus masters outside of the CPU, each | ||
connected to the IPMMU through a port called micro-TLB. | ||
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Required Properties: | ||
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- compatible: Must contain "renesas,ipmmu-vmsa". | ||
- reg: Base address and size of the IPMMU registers. | ||
- interrupts: Specifiers for the MMU fault interrupts. For instances that | ||
support secure mode two interrupts must be specified, for non-secure and | ||
secure mode, in that order. For instances that don't support secure mode a | ||
single interrupt must be specified. | ||
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- #iommu-cells: Must be 1. | ||
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Each bus master connected to an IPMMU must reference the IPMMU in its device | ||
node with the following property: | ||
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- iommus: A reference to the IPMMU in two cells. The first cell is a phandle | ||
to the IPMMU and the second cell the number of the micro-TLB that the | ||
device is connected to. | ||
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Example: R8A7791 IPMMU-MX and VSP1-D0 bus master | ||
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ipmmu_mx: mmu@fe951000 { | ||
compatible = "renasas,ipmmu-vmsa"; | ||
reg = <0 0xfe951000 0 0x1000>; | ||
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, | ||
<0 221 IRQ_TYPE_LEVEL_HIGH>; | ||
#iommu-cells = <1>; | ||
}; | ||
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vsp1@fe928000 { | ||
... | ||
iommus = <&ipmmu_mx 13>; | ||
... | ||
}; |
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