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ice: add admin commands to access cgu configuration
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Add firmware admin command to access clock generation unit
configuration, it is required to enable Extended PTP and SyncE features
in the driver.
Add definitions of possible hardware variations of input and output pins
related to clock generation unit and functions to access the data.

Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
Signed-off-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Arkadiusz Kubalewski authored and David S. Miller committed Sep 17, 2023
1 parent 5f18426 commit 8a3a565
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Showing 8 changed files with 1,385 additions and 33 deletions.
2 changes: 2 additions & 0 deletions drivers/net/ethernet/intel/ice/ice.h
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Original file line number Diff line number Diff line change
Expand Up @@ -198,7 +198,9 @@
enum ice_feature {
ICE_F_DSCP,
ICE_F_PTP_EXTTS,
ICE_F_PHY_RCLK,
ICE_F_SMA_CTRL,
ICE_F_CGU,
ICE_F_GNSS,
ICE_F_ROCE_LAG,
ICE_F_SRIOV_LAG,
Expand Down
246 changes: 244 additions & 2 deletions drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1351,6 +1351,30 @@ struct ice_aqc_set_mac_lb {
u8 reserved[15];
};

/* Set PHY recovered clock output (direct 0x0630) */
struct ice_aqc_set_phy_rec_clk_out {
u8 phy_output;
u8 port_num;
#define ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT 0xFF
u8 flags;
#define ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN BIT(0)
u8 rsvd;
__le32 freq;
u8 rsvd2[6];
__le16 node_handle;
};

/* Get PHY recovered clock output (direct 0x0631) */
struct ice_aqc_get_phy_rec_clk_out {
u8 phy_output;
u8 port_num;
#define ICE_AQC_GET_PHY_REC_CLK_OUT_CURR_PORT 0xFF
u8 flags;
#define ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN BIT(0)
u8 rsvd[11];
__le16 node_handle;
};

struct ice_aqc_link_topo_params {
u8 lport_num;
u8 lport_num_valid;
Expand All @@ -1367,6 +1391,8 @@ struct ice_aqc_link_topo_params {
#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL 9
#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX 10
#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
#define ICE_AQC_LINK_TOPO_NODE_CTX_M \
(0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
Expand Down Expand Up @@ -1403,8 +1429,12 @@ struct ice_aqc_link_topo_addr {
struct ice_aqc_get_link_topo {
struct ice_aqc_link_topo_addr addr;
u8 node_part_num;
#define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
#define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31
#define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
#define ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24
#define ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x25
#define ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY 0x30
#define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31
#define ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47
u8 rsvd[9];
};

Expand Down Expand Up @@ -2125,6 +2155,193 @@ struct ice_aqc_get_pkg_info_resp {
struct ice_aqc_get_pkg_info pkg_info[];
};

/* Get CGU abilities command response data structure (indirect 0x0C61) */
struct ice_aqc_get_cgu_abilities {
u8 num_inputs;
u8 num_outputs;
u8 pps_dpll_idx;
u8 eec_dpll_idx;
__le32 max_in_freq;
__le32 max_in_phase_adj;
__le32 max_out_freq;
__le32 max_out_phase_adj;
u8 cgu_part_num;
u8 rsvd[3];
};

/* Set CGU input config (direct 0x0C62) */
struct ice_aqc_set_cgu_input_config {
u8 input_idx;
u8 flags1;
#define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6)
#define ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7)
u8 flags2;
#define ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5)
#define ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6)
u8 rsvd;
__le32 freq;
__le32 phase_delay;
u8 rsvd2[2];
__le16 node_handle;
};

/* Get CGU input config response descriptor structure (direct 0x0C63) */
struct ice_aqc_get_cgu_input_config {
u8 input_idx;
u8 status;
#define ICE_AQC_GET_CGU_IN_CFG_STATUS_LOS BIT(0)
#define ICE_AQC_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1)
#define ICE_AQC_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2)
#define ICE_AQC_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3)
#define ICE_AQC_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4)
#define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6)
#define ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7)
u8 type;
#define ICE_AQC_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0)
#define ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS BIT(4)
#define ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5)
#define ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY BIT(6)
u8 flags1;
#define ICE_AQC_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0)
#define ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2)
#define ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3)
#define ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7)
__le32 freq;
__le32 phase_delay;
u8 flags2;
#define ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5)
#define ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6)
u8 rsvd[1];
__le16 node_handle;
};

/* Set CGU output config (direct 0x0C64) */
struct ice_aqc_set_cgu_output_config {
u8 output_idx;
u8 flags;
#define ICE_AQC_SET_CGU_OUT_CFG_OUT_EN BIT(0)
#define ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN BIT(1)
#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2)
#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3)
#define ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4)
u8 src_sel;
#define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL ICE_M(0x1F, 0)
u8 rsvd;
__le32 freq;
__le32 phase_delay;
u8 rsvd2[2];
__le16 node_handle;
};

/* Get CGU output config (direct 0x0C65) */
struct ice_aqc_get_cgu_output_config {
u8 output_idx;
u8 flags;
#define ICE_AQC_GET_CGU_OUT_CFG_OUT_EN BIT(0)
#define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN BIT(1)
#define ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2)
u8 src_sel;
#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 0
#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL \
ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT)
#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 5
#define ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE \
ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT)
u8 rsvd;
__le32 freq;
__le32 src_freq;
u8 rsvd2[2];
__le16 node_handle;
};

/* Get CGU DPLL status (direct 0x0C66) */
struct ice_aqc_get_cgu_dpll_status {
u8 dpll_num;
u8 ref_state;
#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0)
#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1)
#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2)
#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3)
#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4)
#define ICE_AQC_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5)
#define ICE_AQC_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6)
u8 dpll_state;
#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0)
#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO BIT(1)
#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2)
#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5)
#define ICE_AQC_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7)
u8 config;
#define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0)
#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT 5
#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE \
ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_FREERUN 0
#define ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \
ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
__le32 phase_offset_h;
__le32 phase_offset_l;
u8 eec_mode;
#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA
#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB
#define ICE_AQC_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF
u8 rsvd[1];
__le16 node_handle;
};

/* Set CGU DPLL config (direct 0x0C67) */
struct ice_aqc_set_cgu_dpll_config {
u8 dpll_num;
u8 ref_state;
#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0)
#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1)
#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2)
#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3)
#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4)
#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5)
#define ICE_AQC_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6)
u8 rsvd;
u8 config;
#define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0)
#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT 5
#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE \
ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)
#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_FREERUN 0
#define ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_AUTOMATIC \
ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)
u8 rsvd2[8];
u8 eec_mode;
u8 rsvd3[1];
__le16 node_handle;
};

/* Set CGU reference priority (direct 0x0C68) */
struct ice_aqc_set_cgu_ref_prio {
u8 dpll_num;
u8 ref_idx;
u8 ref_priority;
u8 rsvd[11];
__le16 node_handle;
};

/* Get CGU reference priority (direct 0x0C69) */
struct ice_aqc_get_cgu_ref_prio {
u8 dpll_num;
u8 ref_idx;
u8 ref_priority; /* Valid only in response */
u8 rsvd[13];
};

/* Get CGU info (direct 0x0C6A) */
struct ice_aqc_get_cgu_info {
__le32 cgu_id;
__le32 cgu_cfg_ver;
__le32 cgu_fw_ver;
u8 node_part_num;
u8 dev_rev;
__le16 node_handle;
};

/* Driver Shared Parameters (direct, 0x0C90) */
struct ice_aqc_driver_shared_params {
u8 set_or_get_op;
Expand Down Expand Up @@ -2194,6 +2411,8 @@ struct ice_aq_desc {
struct ice_aqc_get_phy_caps get_phy;
struct ice_aqc_set_phy_cfg set_phy;
struct ice_aqc_restart_an restart_an;
struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out;
struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out;
struct ice_aqc_gpio read_write_gpio;
struct ice_aqc_sff_eeprom read_write_sff_param;
struct ice_aqc_set_port_id_led set_port_id_led;
Expand Down Expand Up @@ -2234,6 +2453,15 @@ struct ice_aq_desc {
struct ice_aqc_fw_logging fw_logging;
struct ice_aqc_get_clear_fw_log get_clear_fw_log;
struct ice_aqc_download_pkg download_pkg;
struct ice_aqc_set_cgu_input_config set_cgu_input_config;
struct ice_aqc_get_cgu_input_config get_cgu_input_config;
struct ice_aqc_set_cgu_output_config set_cgu_output_config;
struct ice_aqc_get_cgu_output_config get_cgu_output_config;
struct ice_aqc_get_cgu_dpll_status get_cgu_dpll_status;
struct ice_aqc_set_cgu_dpll_config set_cgu_dpll_config;
struct ice_aqc_set_cgu_ref_prio set_cgu_ref_prio;
struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio;
struct ice_aqc_get_cgu_info get_cgu_info;
struct ice_aqc_driver_shared_params drv_shared_params;
struct ice_aqc_set_mac_lb set_mac_lb;
struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
Expand Down Expand Up @@ -2358,6 +2586,8 @@ enum ice_adminq_opc {
ice_aqc_opc_get_link_status = 0x0607,
ice_aqc_opc_set_event_mask = 0x0613,
ice_aqc_opc_set_mac_lb = 0x0620,
ice_aqc_opc_set_phy_rec_clk_out = 0x0630,
ice_aqc_opc_get_phy_rec_clk_out = 0x0631,
ice_aqc_opc_get_link_topo = 0x06E0,
ice_aqc_opc_read_i2c = 0x06E2,
ice_aqc_opc_write_i2c = 0x06E3,
Expand Down Expand Up @@ -2413,6 +2643,18 @@ enum ice_adminq_opc {
ice_aqc_opc_update_pkg = 0x0C42,
ice_aqc_opc_get_pkg_info_list = 0x0C43,

/* 1588/SyncE commands/events */
ice_aqc_opc_get_cgu_abilities = 0x0C61,
ice_aqc_opc_set_cgu_input_config = 0x0C62,
ice_aqc_opc_get_cgu_input_config = 0x0C63,
ice_aqc_opc_set_cgu_output_config = 0x0C64,
ice_aqc_opc_get_cgu_output_config = 0x0C65,
ice_aqc_opc_get_cgu_dpll_status = 0x0C66,
ice_aqc_opc_set_cgu_dpll_config = 0x0C67,
ice_aqc_opc_set_cgu_ref_prio = 0x0C68,
ice_aqc_opc_get_cgu_ref_prio = 0x0C69,
ice_aqc_opc_get_cgu_info = 0x0C6A,

ice_aqc_opc_driver_shared_params = 0x0C90,

/* Standalone Commands/Events */
Expand Down
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