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perf_counter: Rename L2 to LL cache
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The top (fastest) and last level (biggest) caches are the most
interesting ones, performance wise.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
[ Fixed the Nehalem LL table to LLC Reference/Miss events ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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Peter Zijlstra authored and Ingo Molnar committed Jun 11, 2009
1 parent f4dbfa8 commit 8be6e8f
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Showing 8 changed files with 14 additions and 14 deletions.
2 changes: 1 addition & 1 deletion arch/powerpc/kernel/power4-pmu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -561,7 +561,7 @@ static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(OP_WRITE)] = { -1, -1 },
[C(OP_PREFETCH)] = { 0, 0 },
},
[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0, 0 },
[C(OP_WRITE)] = { 0, 0 },
[C(OP_PREFETCH)] = { 0xc34, 0 },
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2 changes: 1 addition & 1 deletion arch/powerpc/kernel/power5+-pmu.c
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Expand Up @@ -632,7 +632,7 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(OP_WRITE)] = { -1, -1 },
[C(OP_PREFETCH)] = { 0, 0 },
},
[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0, 0 },
[C(OP_WRITE)] = { 0, 0 },
[C(OP_PREFETCH)] = { 0xc50c3, 0 },
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2 changes: 1 addition & 1 deletion arch/powerpc/kernel/power5-pmu.c
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Expand Up @@ -574,7 +574,7 @@ static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(OP_WRITE)] = { -1, -1 },
[C(OP_PREFETCH)] = { 0, 0 },
},
[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0, 0x3c309b },
[C(OP_WRITE)] = { 0, 0 },
[C(OP_PREFETCH)] = { 0xc50c3, 0 },
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2 changes: 1 addition & 1 deletion arch/powerpc/kernel/power6-pmu.c
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Expand Up @@ -493,7 +493,7 @@ static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(OP_WRITE)] = { -1, -1 },
[C(OP_PREFETCH)] = { 0x4008c, 0 },
},
[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0x150730, 0x250532 },
[C(OP_WRITE)] = { 0x250432, 0x150432 },
[C(OP_PREFETCH)] = { 0x810a6, 0 },
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2 changes: 1 addition & 1 deletion arch/powerpc/kernel/power7-pmu.c
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Expand Up @@ -320,7 +320,7 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(OP_WRITE)] = { -1, -1 },
[C(OP_PREFETCH)] = { 0x408a, 0 },
},
[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0x6080, 0x6084 },
[C(OP_WRITE)] = { 0x6082, 0x6086 },
[C(OP_PREFETCH)] = { 0, 0 },
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2 changes: 1 addition & 1 deletion arch/powerpc/kernel/ppc970-pmu.c
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Expand Up @@ -445,7 +445,7 @@ static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(OP_WRITE)] = { -1, -1 },
[C(OP_PREFETCH)] = { 0, 0 },
},
[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0, 0 },
[C(OP_WRITE)] = { 0, 0 },
[C(OP_PREFETCH)] = { 0x733, 0 },
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12 changes: 6 additions & 6 deletions arch/x86/kernel/cpu/perf_counter.c
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Original file line number Diff line number Diff line change
Expand Up @@ -131,7 +131,7 @@ static const u64 nehalem_hw_cache_event_ids
[ C(RESULT_MISS) ] = 0x0,
},
},
[ C(L2 ) ] = {
[ C(LL ) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
[ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
Expand All @@ -141,8 +141,8 @@ static const u64 nehalem_hw_cache_event_ids
[ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
},
[ C(OP_PREFETCH) ] = {
[ C(RESULT_ACCESS) ] = 0xc024, /* L2_RQSTS.PREFETCHES */
[ C(RESULT_MISS) ] = 0x8024, /* L2_RQSTS.PREFETCH_MISS */
[ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
[ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
},
},
[ C(DTLB) ] = {
Expand Down Expand Up @@ -222,7 +222,7 @@ static const u64 core2_hw_cache_event_ids
[ C(RESULT_MISS) ] = 0,
},
},
[ C(L2 ) ] = {
[ C(LL ) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
[ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
Expand Down Expand Up @@ -313,7 +313,7 @@ static const u64 atom_hw_cache_event_ids
[ C(RESULT_MISS) ] = 0,
},
},
[ C(L2 ) ] = {
[ C(LL ) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
[ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
Expand Down Expand Up @@ -422,7 +422,7 @@ static const u64 amd_0f_hw_cache_event_ids
[ C(RESULT_MISS) ] = 0,
},
},
[ C(L2 ) ] = {
[ C(LL ) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = 0,
[ C(RESULT_MISS) ] = 0,
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4 changes: 2 additions & 2 deletions include/linux/perf_counter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -56,14 +56,14 @@ enum perf_hw_id {
/*
* Generalized hardware cache counters:
*
* { L1-D, L1-I, L2, LLC, ITLB, DTLB, BPU } x
* { L1-D, L1-I, LLC, ITLB, DTLB, BPU } x
* { read, write, prefetch } x
* { accesses, misses }
*/
enum perf_hw_cache_id {
PERF_COUNT_HW_CACHE_L1D = 0,
PERF_COUNT_HW_CACHE_L1I = 1,
PERF_COUNT_HW_CACHE_L2 = 2,
PERF_COUNT_HW_CACHE_LL = 2,
PERF_COUNT_HW_CACHE_DTLB = 3,
PERF_COUNT_HW_CACHE_ITLB = 4,
PERF_COUNT_HW_CACHE_BPU = 5,
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