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Merge tag 'mvebu-dt64-4.16-2' of git://git.infradead.org/linux-mvebu …
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…into next/dt

Pull "mvebu dt64 for 4.16 (part 2)" from Gregory CLEMENT:

The main change here are the series of commits doing the Armada 7K/8K
CP110 DT de-duplication, they include the de-duplication itself and
small fixes in the device tree files.

Besides them there are 2 other patches:
 - One adding the crypto support for Armada 37xx SoCs
 - An other adding Ethernet aliases on A7K/A8K base boards

* tag 'mvebu-dt64-4.16-2' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: add Ethernet aliases
  arm64: dts: marvell: replace cpm by cp0, cps by cp1
  arm64: dts: marvell: de-duplicate CP110 description
  arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K
  arm64: dts: marvell: use mvebu-icu.h where possible
  arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND
  arm64: dts: marvell: fix typos in comment describing the NAND controller
  arm64: dts: marvell: use lower case for unit address and reg property
  arm64: dts: marvell: fix watchdog unit address in Armada AP806
  arm64: dts: marvell: armada-37xx: add a crypto node
  ARM64: dts: marvell: armada-cp110: Fix clock resources for various node
  ARM: dts: kirkwood: fix pin-muxing of MPP7 on OpenBlocks A7
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Arnd Bergmann committed Jan 5, 2018
2 parents c503f59 + 474c588 commit 8c11fcc
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Showing 14 changed files with 678 additions and 1,027 deletions.
10 changes: 8 additions & 2 deletions arch/arm/boot/dts/kirkwood-openblocks_a7.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,8 @@
};

pinctrl: pin-controller@10000 {
pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header
&pmx_gpio_header_gpo>;
pinctrl-names = "default";

pmx_uart0: pmx-uart0 {
Expand Down Expand Up @@ -85,11 +86,16 @@
* ground.
*/
pmx_gpio_header: pmx-gpio-header {
marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28",
marvell,pins = "mpp17", "mpp29", "mpp28",
"mpp35", "mpp34", "mpp40";
marvell,function = "gpio";
};

pmx_gpio_header_gpo: pxm-gpio-header-gpo {
marvell,pins = "mpp7";
marvell,function = "gpo";
};

pmx_gpio_init: pmx-init {
marvell,pins = "mpp38";
marvell,function = "gpio";
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14 changes: 14 additions & 0 deletions arch/arm64/boot/dts/marvell/armada-37xx.dtsi
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Expand Up @@ -316,6 +316,20 @@
};
};

crypto: crypto@90000 {
compatible = "inside-secure,safexcel-eip97";
reg = <0x90000 0x20000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&nb_periph_clk 15>;
};

sdhci1: sdhci@d0000 {
compatible = "marvell,armada-3700-sdhci",
"marvell,sdhci-xenon";
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52 changes: 29 additions & 23 deletions arch/arm64/boot/dts/marvell/armada-7040-db.dts
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Expand Up @@ -61,7 +61,13 @@
reg = <0x0 0x0 0x0 0x80000000>;
};

cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
};

cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3h0-vbus";
regulator-min-microvolt = <5000000>;
Expand All @@ -70,7 +76,7 @@
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
};

cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3h1-vbus";
regulator-min-microvolt = <5000000>;
Expand All @@ -79,14 +85,14 @@
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};

cpm_usb3_0_phy: cpm-usb3-0-phy {
cp0_usb3_0_phy: cp0-usb3-0-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cpm_reg_usb3_0_vbus>;
vcc-supply = <&cp0_reg_usb3_0_vbus>;
};

cpm_usb3_1_phy: cpm-usb3-1-phy {
cp0_usb3_1_phy: cp0-usb3-1-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&cpm_reg_usb3_1_vbus>;
vcc-supply = <&cp0_reg_usb3_1_vbus>;
};
};

Expand Down Expand Up @@ -129,11 +135,11 @@
};


&cpm_pcie2 {
&cp0_pcie2 {
status = "okay";
};

&cpm_i2c0 {
&cp0_i2c0 {
status = "okay";
clock-frequency = <100000>;

Expand All @@ -156,7 +162,7 @@
};
};

&cpm_nand {
&cp0_nand {
/*
* SPI on CPM and NAND have common pins on this board. We can
* use only one at a time. To enable the NAND (whihch will
Expand Down Expand Up @@ -186,7 +192,7 @@
};


&cpm_spi1 {
&cp0_spi1 {
status = "okay";

spi-flash@0 {
Expand Down Expand Up @@ -214,17 +220,17 @@
};
};

&cpm_sata0 {
&cp0_sata0 {
status = "okay";
};

&cpm_usb3_0 {
usb-phy = <&cpm_usb3_0_phy>;
&cp0_usb3_0 {
usb-phy = <&cp0_usb3_0_phy>;
status = "okay";
};

&cpm_usb3_1 {
usb-phy = <&cpm_usb3_1_phy>;
&cp0_usb3_1 {
usb-phy = <&cp0_usb3_1_phy>;
status = "okay";
};

Expand All @@ -235,14 +241,14 @@
non-removable;
};

&cpm_sdhci0 {
&cp0_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
};

&cpm_mdio {
&cp0_mdio {
status = "okay";

phy0: ethernet-phy@0 {
Expand All @@ -253,28 +259,28 @@
};
};

&cpm_ethernet {
&cp0_ethernet {
status = "okay";
};

&cpm_eth0 {
&cp0_eth0 {
status = "okay";
/* Network PHY */
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy2 0>;
phys = <&cp0_comphy2 0>;
};

&cpm_eth1 {
&cp0_eth1 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy0 1>;
phys = <&cp0_comphy0 1>;
};

&cpm_eth2 {
&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
Expand Down
37 changes: 29 additions & 8 deletions arch/arm64/boot/dts/marvell/armada-70x0.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -44,25 +44,46 @@
* Device Tree file for the Armada 70x0 SoC
*/

#include "armada-cp110-master.dtsi"

/ {
aliases {
gpio1 = &cpm_gpio1;
gpio2 = &cpm_gpio2;
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
spi1 = &cp0_spi0;
spi2 = &cp0_spi1;
};
};

&cpm_gpio1 {
/*
* Instantiate the CP110
*/
#define CP110_NAME cp0
#define CP110_BASE f2000000
#define CP110_PCIE_IO_BASE 0xf9000000
#define CP110_PCIE_MEM_BASE 0xf6000000
#define CP110_PCIE0_BASE f2600000
#define CP110_PCIE1_BASE f2620000
#define CP110_PCIE2_BASE f2640000

#include "armada-cp110.dtsi"

#undef CP110_NAME
#undef CP110_BASE
#undef CP110_PCIE_IO_BASE
#undef CP110_PCIE_MEM_BASE
#undef CP110_PCIE0_BASE
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE

&cp0_gpio1 {
status = "okay";
};

&cpm_gpio2 {
&cp0_gpio2 {
status = "okay";
};

&cpm_syscon0 {
cpm_pinctrl: pinctrl {
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";

nand_pins: nand-pins {
Expand Down
2 changes: 1 addition & 1 deletion arch/arm64/boot/dts/marvell/armada-8020.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,6 @@
* oscillator so this one is let enabled.
*/

&cpm_rtc {
&cp0_rtc {
status = "disabled";
};
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