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Merge branch 'drm-next-3.13' of git://people.freedesktop.org/~agd5f/l…
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…inux into drm-next

A few more patches for 3.13.  The big one here is Hawaii support.
I wanted to get that out sooner, but was sick earlier this week.  That
said, it's mostly self contained, so it shouldn't impact other asics.
The rest are just bug fixes and a merge fix.

* 'drm-next-3.13' of git://people.freedesktop.org/~agd5f/linux: (23 commits)
  Revert "drm/radeon/audio: don't set speaker allocation on DCE4+"
  drm/radeon/audio: improve ACR calculation
  drm/radeon/audio: correct ACR table
  drm/radeon: fix mismerge of drm-next with 3.12
  drm/radeon: add pci ids for hawaii
  drm/radeon: fill in radeon_asic_init for hawaii
  drm/radeon: modesetting updates for hawaii
  drm/radeon: atombios.h updates for hawaii
  drm/radeon: update cik_get_csb_buffer for hawaii
  drm/radeon: add hawaii dpm support
  drm/radeon/cik: add hawaii UVD support
  drm/radeon: update firmware loading for hawaii
  drm/radeon: update rb setup for hawaii
  drm/radeon: add golden register settings for hawaii
  drm/radeon: update cik_tiling_mode_table_init() for hawaii
  drm/radeon: minor updates to cik.c for hawaii
  drm/radeon: update cik_gpu_init() for hawaii
  drm/radeon: add Hawaii chip family
  drm/radeon: fix-up some float to fixed conversion thinkos
  drm/radeon: use HDP_MEM_COHERENCY_FLUSH_CNTL for sdma as well
  ...
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Dave Airlie committed Nov 10, 2013
2 parents c4b3a81 + 28ed756 commit 8d0a221
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Showing 21 changed files with 882 additions and 156 deletions.
127 changes: 115 additions & 12 deletions drivers/gpu/drm/radeon/atombios.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1711,7 +1711,9 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V6
#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40
Expand Down Expand Up @@ -2223,7 +2225,7 @@ typedef struct _SET_VOLTAGE_PARAMETERS_V2
USHORT usVoltageLevel; // real voltage level
}SET_VOLTAGE_PARAMETERS_V2;


// used by both SetVoltageTable v1.3 and v1.4
typedef struct _SET_VOLTAGE_PARAMETERS_V1_3
{
UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
Expand Down Expand Up @@ -2290,15 +2292,36 @@ typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
#define ATOM_GET_VOLTAGE_VID 0x00
#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03
#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04
// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info

// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
// undefined power state

#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13

// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
{
UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;

// New in GetVoltageInfo v1.2 ucVoltageMode
#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09

// New Added from CI Hawaii for EVV feature
typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
{
USHORT usVoltageLevel; // real voltage level in unit of mv
USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
ULONG ulReseved;
}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;

/****************************************************************************/
// Structures used by TVEncoderControlTable
/****************************************************************************/
Expand Down Expand Up @@ -3864,6 +3887,8 @@ typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
#define PP_AC_DC_SWITCH_GPIO_PINID 60
//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
#define VDDC_VRHOT_GPIO_PINID 61
//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled
#define VDDC_PCC_GPIO_PINID 62

typedef struct _ATOM_GPIO_PIN_LUT
{
Expand Down Expand Up @@ -4169,10 +4194,10 @@ typedef struct _ATOM_COMMON_RECORD_HEADER
#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19
#define ATOM_ENCODER_CAP_RECORD_TYPE 20

#define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21

//Must be updated when new record type is added,equal to that record definition!
#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE
#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_BRACKET_LAYOUT_RECORD_TYPE

typedef struct _ATOM_I2C_RECORD
{
Expand Down Expand Up @@ -4397,6 +4422,31 @@ typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
USHORT usReserved;
}ATOM_CONNECTOR_REMOTE_CAP_RECORD;

typedef struct _ATOM_CONNECTOR_LAYOUT_INFO
{
USHORT usConnectorObjectId;
UCHAR ucConnectorType;
UCHAR ucPosition;
}ATOM_CONNECTOR_LAYOUT_INFO;

// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
#define CONNECTOR_TYPE_DVI_D 1
#define CONNECTOR_TYPE_DVI_I 2
#define CONNECTOR_TYPE_VGA 3
#define CONNECTOR_TYPE_HDMI 4
#define CONNECTOR_TYPE_DISPLAY_PORT 5
#define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6

typedef struct _ATOM_BRACKET_LAYOUT_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucLength;
UCHAR ucWidth;
UCHAR ucConnNum;
UCHAR ucReserved;
ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1];
}ATOM_BRACKET_LAYOUT_RECORD;

/****************************************************************************/
// ASIC voltage data table
/****************************************************************************/
Expand Down Expand Up @@ -4524,8 +4574,9 @@ typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3
#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3
#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
#define VOLTAGE_OBJ_EVV 8
#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3

typedef struct _VOLTAGE_LUT_ENTRY_V2
Expand All @@ -4552,6 +4603,10 @@ typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3
VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff
}ATOM_I2C_VOLTAGE_OBJECT_V3;

// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
#define VOLTAGE_DATA_ONE_BYTE 0
#define VOLTAGE_DATA_TWO_BYTE 1

typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3
{
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
Expand Down Expand Up @@ -4584,7 +4639,8 @@ typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3
// 1:0 – offset trim,
USHORT usLoadLine_PSI;
// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31
UCHAR ucReserved[2];
UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31
UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31
ULONG ulReserved;
}ATOM_SVID2_VOLTAGE_OBJECT_V3;

Expand Down Expand Up @@ -4637,6 +4693,49 @@ typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1
USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
}ATOM_ASIC_PROFILING_INFO_V2_1;

typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1
{
ATOM_COMMON_TABLE_HEADER asHeader;
ULONG ulEvvDerateTdp;
ULONG ulEvvDerateTdc;
ULONG ulBoardCoreTemp;
ULONG ulMaxVddc;
ULONG ulMinVddc;
ULONG ulLoadLineSlop;
ULONG ulLeakageTemp;
ULONG ulLeakageVoltage;
ULONG ulCACmEncodeRange;
ULONG ulCACmEncodeAverage;
ULONG ulCACbEncodeRange;
ULONG ulCACbEncodeAverage;
ULONG ulKt_bEncodeRange;
ULONG ulKt_bEncodeAverage;
ULONG ulKv_mEncodeRange;
ULONG ulKv_mEncodeAverage;
ULONG ulKv_bEncodeRange;
ULONG ulKv_bEncodeAverage;
ULONG ulLkgEncodeLn_MaxDivMin;
ULONG ulLkgEncodeMin;
ULONG ulEfuseLogisticAlpha;
USHORT usPowerDpm0;
USHORT usCurrentDpm0;
USHORT usPowerDpm1;
USHORT usCurrentDpm1;
USHORT usPowerDpm2;
USHORT usCurrentDpm2;
USHORT usPowerDpm3;
USHORT usCurrentDpm3;
USHORT usPowerDpm4;
USHORT usCurrentDpm4;
USHORT usPowerDpm5;
USHORT usCurrentDpm5;
USHORT usPowerDpm6;
USHORT usCurrentDpm6;
USHORT usPowerDpm7;
USHORT usCurrentDpm7;
}ATOM_ASIC_PROFILING_INFO_V3_1;


typedef struct _ATOM_POWER_SOURCE_OBJECT
{
UCHAR ucPwrSrcId; // Power source
Expand Down Expand Up @@ -5808,6 +5907,8 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C
#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0
#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01
#define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02
#define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200
#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF

#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
Expand Down Expand Up @@ -6242,6 +6343,7 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE
#define _128Mx32 0x53
#define _256Mx8 0x61
#define _256Mx16 0x62
#define _512Mx8 0x71

#define SAMSUNG 0x1
#define INFINEON 0x2
Expand Down Expand Up @@ -6987,9 +7089,10 @@ typedef struct _ATOM_DISP_OUT_INFO_V3
UCHAR ucMaxDispEngineNum;
UCHAR ucMaxActiveDispEngineNum;
UCHAR ucMaxPPLLNum;
UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
UCHAR ucReserved[3];
ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only
UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
UCHAR ucDispCaps;
UCHAR ucReserved[2];
ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only
}ATOM_DISP_OUT_INFO_V3;

//ucDispCaps
Expand Down
19 changes: 18 additions & 1 deletion drivers/gpu/drm/radeon/atombios_crtc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1910,6 +1910,21 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
int i;

atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
if (crtc->fb) {
int r;
struct radeon_framebuffer *radeon_fb;
struct radeon_bo *rbo;

radeon_fb = to_radeon_framebuffer(crtc->fb);
rbo = gem_to_radeon_bo(radeon_fb->obj);
r = radeon_bo_reserve(rbo, false);
if (unlikely(r))
DRM_ERROR("failed to reserve rbo before unpin\n");
else {
radeon_bo_unpin(rbo);
radeon_bo_unreserve(rbo);
}
}
/* disable the GRPH */
if (ASIC_IS_DCE4(rdev))
WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
Expand Down Expand Up @@ -1940,7 +1955,9 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
break;
case ATOM_PPLL0:
/* disable the ppll */
if ((rdev->family == CHIP_ARUBA) || (rdev->family == CHIP_BONAIRE))
if ((rdev->family == CHIP_ARUBA) ||
(rdev->family == CHIP_BONAIRE) ||
(rdev->family == CHIP_HAWAII))
atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
break;
Expand Down
58 changes: 47 additions & 11 deletions drivers/gpu/drm/radeon/ci_dpm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,20 @@
#define VOLTAGE_VID_OFFSET_SCALE1 625
#define VOLTAGE_VID_OFFSET_SCALE2 100

static const struct ci_pt_defaults defaults_hawaii_xt =
{
1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
{ 0x84, 0x0, 0x0, 0x7F, 0x0, 0x0, 0x5A, 0x60, 0x51, 0x8E, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
{ 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
};

static const struct ci_pt_defaults defaults_hawaii_pro =
{
1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
{ 0x93, 0x0, 0x0, 0x97, 0x0, 0x0, 0x6B, 0x60, 0x51, 0x95, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
{ 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
};

static const struct ci_pt_defaults defaults_bonaire_xt =
{
1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
Expand Down Expand Up @@ -187,22 +201,38 @@ static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
struct ci_power_info *pi = ci_get_pi(rdev);

switch (rdev->pdev->device) {
case 0x6650:
case 0x6658:
case 0x665C:
default:
case 0x6650:
case 0x6658:
case 0x665C:
default:
pi->powertune_defaults = &defaults_bonaire_xt;
break;
case 0x6651:
case 0x665D:
case 0x6651:
case 0x665D:
pi->powertune_defaults = &defaults_bonaire_pro;
break;
case 0x6640:
case 0x6640:
pi->powertune_defaults = &defaults_saturn_xt;
break;
case 0x6641:
case 0x6641:
pi->powertune_defaults = &defaults_saturn_pro;
break;
case 0x67B8:
case 0x67B0:
case 0x67A0:
case 0x67A1:
case 0x67A2:
case 0x67A8:
case 0x67A9:
case 0x67AA:
case 0x67B9:
case 0x67BE:
pi->powertune_defaults = &defaults_hawaii_xt;
break;
case 0x67BA:
case 0x67B1:
pi->powertune_defaults = &defaults_hawaii_pro;
break;
}

pi->dte_tj_offset = 0;
Expand Down Expand Up @@ -5142,9 +5172,15 @@ int ci_dpm_init(struct radeon_device *rdev)
rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;

pi->thermal_temp_setting.temperature_low = 99500;
pi->thermal_temp_setting.temperature_high = 100000;
pi->thermal_temp_setting.temperature_shutdown = 104000;
if (rdev->family == CHIP_HAWAII) {
pi->thermal_temp_setting.temperature_low = 94500;
pi->thermal_temp_setting.temperature_high = 95000;
pi->thermal_temp_setting.temperature_shutdown = 104000;
} else {
pi->thermal_temp_setting.temperature_low = 99500;
pi->thermal_temp_setting.temperature_high = 100000;
pi->thermal_temp_setting.temperature_shutdown = 104000;
}

pi->uvd_enabled = false;

Expand Down
4 changes: 4 additions & 0 deletions drivers/gpu/drm/radeon/ci_smc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -217,6 +217,10 @@ int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)
ucode_start_address = BONAIRE_SMC_UCODE_START;
ucode_size = BONAIRE_SMC_UCODE_SIZE;
break;
case CHIP_HAWAII:
ucode_start_address = HAWAII_SMC_UCODE_START;
ucode_size = HAWAII_SMC_UCODE_SIZE;
break;
default:
DRM_ERROR("unknown asic in smc ucode loader\n");
BUG();
Expand Down
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