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Merge branches 'clk-nvidia', 'clk-rockchip', 'clk-at91' and 'clk-vc5'…
… into clk-next - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators * clk-nvidia: clk: tegra: fix old-style declaration clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock soc/tegra: fuse: Enable fuse clock on suspend for Tegra124 soc/tegra: fuse: Add runtime PM support soc/tegra: fuse: Clear fuse->clk on driver probe failure soc/tegra: pmc: Prevent racing with cpuilde driver soc/tegra: bpmp: Remove unused including <linux/version.h> * clk-rockchip: clk: rockchip: make rk3308 ddrphy4x clock critical clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema clk: rockchip: Add support for hclk_sfc on rk3036 clk: rockchip: rk3036: fix up the sclk_sfc parent error clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036 * clk-at91: clk: at91: clk-generated: Limit the requested rate to our range * clk-vc5: clk: vc5: Add properties for configuring SD/OE behavior clk: vc5: Use dev_err_probe dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
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Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
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Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
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# SPDX-License-Identifier: GPL-2.0-only | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Rockchip RK3399 Clock and Reset Unit | ||
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||
maintainers: | ||
- Xing Zheng <zhengxing@rock-chips.com> | ||
- Heiko Stuebner <heiko@sntech.de> | ||
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||
description: | | ||
The RK3399 clock controller generates and supplies clock to various | ||
controllers within the SoC and also implements a reset controller for SoC | ||
peripherals. | ||
Each clock is assigned an identifier and client nodes can use this identifier | ||
to specify the clock which they consume. All available clocks are defined as | ||
preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be | ||
used in device tree sources. Similar macros exist for the reset sources in | ||
these files. | ||
There are several clocks that are generated outside the SoC. It is expected | ||
that they are defined using standard clock bindings with following | ||
clock-output-names: | ||
- "xin24m" - crystal input - required, | ||
- "xin32k" - rtc clock - optional, | ||
- "clkin_gmac" - external GMAC clock - optional, | ||
- "clkin_i2s" - external I2S clock - optional, | ||
- "pclkin_cif" - external ISP clock - optional, | ||
- "clk_usbphy0_480m" - output clock of the pll in the usbphy0 | ||
- "clk_usbphy1_480m" - output clock of the pll in the usbphy1 | ||
properties: | ||
compatible: | ||
enum: | ||
- rockchip,rk3399-pmucru | ||
- rockchip,rk3399-cru | ||
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reg: | ||
maxItems: 1 | ||
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"#clock-cells": | ||
const: 1 | ||
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"#reset-cells": | ||
const: 1 | ||
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clocks: | ||
minItems: 1 | ||
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assigned-clocks: | ||
minItems: 1 | ||
maxItems: 64 | ||
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assigned-clock-parents: | ||
minItems: 1 | ||
maxItems: 64 | ||
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assigned-clock-rates: | ||
minItems: 1 | ||
maxItems: 64 | ||
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rockchip,grf: | ||
$ref: /schemas/types.yaml#/definitions/phandle | ||
description: > | ||
phandle to the syscon managing the "general register files". It is used | ||
for GRF muxes, if missing any muxes present in the GRF will not be | ||
available. | ||
required: | ||
- compatible | ||
- reg | ||
- "#clock-cells" | ||
- "#reset-cells" | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
pmucru: pmu-clock-controller@ff750000 { | ||
compatible = "rockchip,rk3399-pmucru"; | ||
reg = <0xff750000 0x1000>; | ||
#clock-cells = <1>; | ||
#reset-cells = <1>; | ||
}; | ||
- | | ||
cru: clock-controller@ff760000 { | ||
compatible = "rockchip,rk3399-cru"; | ||
reg = <0xff760000 0x1000>; | ||
#clock-cells = <1>; | ||
#reset-cells = <1>; | ||
}; |
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