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Merge branches 'clk-nvidia', 'clk-rockchip', 'clk-at91' and 'clk-vc5'…
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… into clk-next

 - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators

* clk-nvidia:
  clk: tegra: fix old-style declaration
  clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock
  soc/tegra: fuse: Enable fuse clock on suspend for Tegra124
  soc/tegra: fuse: Add runtime PM support
  soc/tegra: fuse: Clear fuse->clk on driver probe failure
  soc/tegra: pmc: Prevent racing with cpuilde driver
  soc/tegra: bpmp: Remove unused including <linux/version.h>

* clk-rockchip:
  clk: rockchip: make rk3308 ddrphy4x clock critical
  clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types
  dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema
  clk: rockchip: Add support for hclk_sfc on rk3036
  clk: rockchip: rk3036: fix up the sclk_sfc parent error
  clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036

* clk-at91:
  clk: at91: clk-generated: Limit the requested rate to our range

* clk-vc5:
  clk: vc5: Add properties for configuring SD/OE behavior
  clk: vc5: Use dev_err_probe
  dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
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Stephen Boyd committed Sep 1, 2021
5 parents 1faa7cb + 2711544 + 1d07010 + af7651e + d83e561 commit 8fb59ce
Showing 21 changed files with 279 additions and 106 deletions.
40 changes: 40 additions & 0 deletions Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
Original file line number Diff line number Diff line change
@@ -30,6 +30,20 @@ description: |
3 -- OUT3
4 -- OUT4
The idt,shutdown and idt,output-enable-active properties control the
SH (en_global_shutdown) and SP bits of the Primary Source and Shutdown
Register, respectively. Their behavior is summarized by the following
table:
SH SP Output when the SD/OE pin is Low/High
== == =====================================
0 0 Active/Inactive
0 1 Inactive/Active
1 0 Active/Shutdown
1 1 Inactive/Shutdown
The case where SH and SP are both 1 is likely not very interesting.
maintainers:
- Luca Ceresoli <luca@lucaceresoli.net>

@@ -64,6 +78,26 @@ properties:
maximum: 22760
description: Optional load capacitor for XTAL1 and XTAL2

idt,shutdown:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
If 1, this enables the shutdown functionality: the chip will be
shut down if the SD/OE pin is driven high. If 0, this disables the
shutdown functionality: the chip will never be shut down based on
the value of the SD/OE pin. This property corresponds to the SH
bit of the Primary Source and Shutdown Register.
idt,output-enable-active:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
If 1, this enables output when the SD/OE pin is high, and disables
output when the SD/OE pin is low. If 0, this disables output when
the SD/OE pin is high, and enables output when the SD/OE pin is
low. This corresponds to the SP bit of the Primary Source and
Shutdown Register.
patternProperties:
"^OUT[1-4]$":
type: object
@@ -90,6 +124,8 @@ required:
- compatible
- reg
- '#clock-cells'
- idt,shutdown
- idt,output-enable-active

allOf:
- if:
@@ -139,6 +175,10 @@ examples:
clocks = <&ref25m>;
clock-names = "xin";
/* Set the SD/OE pin's settings */
idt,shutdown = <0>;
idt,output-enable-active = <0>;
OUT1 {
idt,mode = <VC5_CMOSD>;
idt,voltage-microvolt = <1800000>;
68 changes: 0 additions & 68 deletions Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt

This file was deleted.

92 changes: 92 additions & 0 deletions Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,92 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3399 Clock and Reset Unit

maintainers:
- Xing Zheng <zhengxing@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>

description: |
The RK3399 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
used in device tree sources. Similar macros exist for the reset sources in
these files.
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "xin32k" - rtc clock - optional,
- "clkin_gmac" - external GMAC clock - optional,
- "clkin_i2s" - external I2S clock - optional,
- "pclkin_cif" - external ISP clock - optional,
- "clk_usbphy0_480m" - output clock of the pll in the usbphy0
- "clk_usbphy1_480m" - output clock of the pll in the usbphy1
properties:
compatible:
enum:
- rockchip,rk3399-pmucru
- rockchip,rk3399-cru

reg:
maxItems: 1

"#clock-cells":
const: 1

"#reset-cells":
const: 1

clocks:
minItems: 1

assigned-clocks:
minItems: 1
maxItems: 64

assigned-clock-parents:
minItems: 1
maxItems: 64

assigned-clock-rates:
minItems: 1
maxItems: 64

rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description: >
phandle to the syscon managing the "general register files". It is used
for GRF muxes, if missing any muxes present in the GRF will not be
available.
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"

additionalProperties: false

examples:
- |
pmucru: pmu-clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0xff750000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- |
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3399-cru";
reg = <0xff760000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
2 changes: 1 addition & 1 deletion arch/arm/mach-tegra/pm.c
Original file line number Diff line number Diff line change
@@ -403,7 +403,7 @@ static const struct platform_suspend_ops tegra_suspend_ops = {
.enter = tegra_suspend_enter,
};

void __init tegra_init_suspend(void)
void tegra_pm_init_suspend(void)
{
enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();

6 changes: 0 additions & 6 deletions arch/arm/mach-tegra/pm.h
Original file line number Diff line number Diff line change
@@ -25,10 +25,4 @@ void tegra30_sleep_core_init(void);

extern void (*tegra_tear_down_cpu)(void);

#ifdef CONFIG_PM_SLEEP
void tegra_init_suspend(void);
#else
static inline void tegra_init_suspend(void) {}
#endif

#endif /* _MACH_TEGRA_PM_H_ */
2 changes: 0 additions & 2 deletions arch/arm/mach-tegra/tegra.c
Original file line number Diff line number Diff line change
@@ -84,8 +84,6 @@ static void __init tegra_dt_init(void)

static void __init tegra_dt_init_late(void)
{
tegra_init_suspend();

if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
of_machine_is_compatible("compal,paz00"))
tegra_paz00_wifikill_init();
6 changes: 6 additions & 0 deletions drivers/clk/at91/clk-generated.c
Original file line number Diff line number Diff line change
@@ -128,6 +128,12 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
int i;
u32 div;

/* do not look for a rate that is outside of our range */
if (gck->range.max && req->rate > gck->range.max)
req->rate = gck->range.max;
if (gck->range.min && req->rate < gck->range.min)
req->rate = gck->range.min;

for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
if (gck->chg_pid == i)
continue;
42 changes: 33 additions & 9 deletions drivers/clk/clk-versaclock5.c
Original file line number Diff line number Diff line change
@@ -907,6 +907,7 @@ static const struct of_device_id clk_vc5_of_match[];

static int vc5_probe(struct i2c_client *client, const struct i2c_device_id *id)
{
unsigned int oe, sd, src_mask = 0, src_val = 0;
struct vc5_driver_data *vc5;
struct clk_init_data init;
const char *parent_names[2];
@@ -930,11 +931,33 @@ static int vc5_probe(struct i2c_client *client, const struct i2c_device_id *id)
return -EPROBE_DEFER;

vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
if (IS_ERR(vc5->regmap)) {
dev_err(&client->dev, "failed to allocate register map\n");
return PTR_ERR(vc5->regmap);
if (IS_ERR(vc5->regmap))
return dev_err_probe(&client->dev, PTR_ERR(vc5->regmap),
"failed to allocate register map\n");

ret = of_property_read_u32(client->dev.of_node, "idt,shutdown", &sd);
if (!ret) {
src_mask |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN;
if (sd)
src_val |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN;
} else if (ret != -EINVAL) {
return dev_err_probe(&client->dev, ret,
"could not read idt,shutdown\n");
}

ret = of_property_read_u32(client->dev.of_node,
"idt,output-enable-active", &oe);
if (!ret) {
src_mask |= VC5_PRIM_SRC_SHDN_SP;
if (oe)
src_val |= VC5_PRIM_SRC_SHDN_SP;
} else if (ret != -EINVAL) {
return dev_err_probe(&client->dev, ret,
"could not read idt,output-enable-active\n");
}

regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask, src_val);

/* Register clock input mux */
memset(&init, 0, sizeof(init));

@@ -957,10 +980,9 @@ static int vc5_probe(struct i2c_client *client, const struct i2c_device_id *id)
__clk_get_name(vc5->pin_clkin);
}

if (!init.num_parents) {
dev_err(&client->dev, "no input clock specified!\n");
return -EINVAL;
}
if (!init.num_parents)
return dev_err_probe(&client->dev, -EINVAL,
"no input clock specified!\n");

/* Configure Optional Loading Capacitance for external XTAL */
if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) {
@@ -1099,14 +1121,16 @@ static int vc5_probe(struct i2c_client *client, const struct i2c_device_id *id)

ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
if (ret) {
dev_err(&client->dev, "unable to add clk provider\n");
dev_err_probe(&client->dev, ret,
"unable to add clk provider\n");
goto err_clk;
}

return 0;

err_clk_register:
dev_err(&client->dev, "unable to register %s\n", init.name);
dev_err_probe(&client->dev, ret,
"unable to register %s\n", init.name);
kfree(init.name); /* clock framework made a copy of the name */
err_clk:
if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
2 changes: 1 addition & 1 deletion drivers/clk/rockchip/clk-pll.c
Original file line number Diff line number Diff line change
@@ -940,7 +940,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
switch (pll_type) {
case pll_rk3036:
case pll_rk3328:
if (!pll->rate_table || IS_ERR(ctx->grf))
if (!pll->rate_table)
init.ops = &rockchip_rk3036_pll_clk_norate_ops;
else
init.ops = &rockchip_rk3036_pll_clk_ops;
5 changes: 3 additions & 2 deletions drivers/clk/rockchip/clk-rk3036.c
Original file line number Diff line number Diff line change
@@ -121,6 +121,7 @@ PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };

PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };

PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
@@ -340,7 +341,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 4, GFLAGS),

COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0,
RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 5, GFLAGS),

@@ -403,7 +404,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),

/* pclk_peri gates */
1 change: 1 addition & 0 deletions drivers/clk/rockchip/clk-rk3308.c
Original file line number Diff line number Diff line change
@@ -911,6 +911,7 @@ static const char *const rk3308_critical_clocks[] __initconst = {
"hclk_audio",
"pclk_audio",
"sclk_ddrc",
"clk_ddrphy4x",
};

static void __init rk3308_clk_init(struct device_node *np)
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