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ARM: mvebu: Add Armada 388 General Purpose Development Board support
The A388-GP is a board produced by Marvell that holds - 1 PCIe slot - 2 mini PCIe slot (one of them is multiplexed with the PCIe slot, muxing is selected through the GPIO expander) - 1 16MB SPI-NOR - 2 Gigabit Ethernet ports - 4 SATA ports (2 of them are multiplexed with the mini PCIe slots, muxing is selected through the GPIO expander) - 1 SDIO slot - 1 USB3 port - 2 USB2 port - 2 GPIO/interrupts expander on I2C Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
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/* | ||
* Device Tree file for Marvell Armada 385 development board | ||
* (RD-88F6820-GP) | ||
* | ||
* Copyright (C) 2014 Marvell | ||
* | ||
* Gregory CLEMENT <gregory.clement@free-electrons.com> | ||
* | ||
* This file is dual-licensed: you can use it either under the terms | ||
* of the GPL or the X11 license, at your option. Note that this dual | ||
* licensing only applies to this file, and not this project as a | ||
* whole. | ||
* | ||
* a) This file is licensed under the terms of the GNU General Public | ||
* License version 2. This program is licensed "as is" without | ||
* any warranty of any kind, whether express or implied. | ||
* | ||
* Or, alternatively, | ||
* | ||
* b) Permission is hereby granted, free of charge, to any person | ||
* obtaining a copy of this software and associated documentation | ||
* files (the "Software"), to deal in the Software without | ||
* restriction, including without limitation the rights to use, | ||
* copy, modify, merge, publish, distribute, sublicense, and/or | ||
* sell copies of the Software, and to permit persons to whom the | ||
* Software is furnished to do so, subject to the following | ||
* conditions: | ||
* | ||
* The above copyright notice and this permission notice shall be | ||
* included in all copies or substantial portions of the Software. | ||
* | ||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | ||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | ||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | ||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
* OTHER DEALINGS IN THE SOFTWARE. | ||
*/ | ||
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/dts-v1/; | ||
#include "armada-388.dtsi" | ||
#include <dt-bindings/gpio/gpio.h> | ||
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/ { | ||
model = "Marvell Armada 385 GP"; | ||
compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380"; | ||
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chosen { | ||
bootargs = "console=ttyS0,115200"; | ||
stdout-path = &uart0; | ||
}; | ||
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memory { | ||
device_type = "memory"; | ||
reg = <0x00000000 0x80000000>; /* 2 GB */ | ||
}; | ||
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soc { | ||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 | ||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; | ||
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internal-regs { | ||
spi@10600 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&spi0_pins>; | ||
status = "okay"; | ||
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spi-flash@0 { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
compatible = "st,m25p128"; | ||
reg = <0>; /* Chip select 0 */ | ||
spi-max-frequency = <50000000>; | ||
m25p,fast-read; | ||
}; | ||
}; | ||
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i2c@11000 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&i2c0_pins>; | ||
status = "okay"; | ||
clock-frequency = <100000>; | ||
/* | ||
* The EEPROM located at adresse 54 is needed | ||
* for the boot - DO NOT ERASE IT - | ||
*/ | ||
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expander0: pca9555@20 { | ||
compatible = "nxp,pca9555"; | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&pca0_pins>; | ||
interrupt-parent = <&gpio0>; | ||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>; | ||
gpio-controller; | ||
#gpio-cells = <2>; | ||
interrupt-controller; | ||
#interrupt-cells = <2>; | ||
reg = <0x20>; | ||
}; | ||
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expander1: pca9555@21 { | ||
compatible = "nxp,pca9555"; | ||
pinctrl-names = "default"; | ||
interrupt-parent = <&gpio0>; | ||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>; | ||
gpio-controller; | ||
#gpio-cells = <2>; | ||
interrupt-controller; | ||
#interrupt-cells = <2>; | ||
reg = <0x21>; | ||
}; | ||
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}; | ||
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serial@12000 { | ||
/* | ||
* Exported on the micro USB connector CON16 | ||
* through an FTDI | ||
*/ | ||
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pinctrl-names = "default"; | ||
pinctrl-0 = <&uart0_pins>; | ||
status = "okay"; | ||
}; | ||
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/* GE1 CON15 */ | ||
ethernet@30000 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&ge1_rgmii_pins>; | ||
status = "okay"; | ||
phy = <&phy1>; | ||
phy-mode = "rgmii-id"; | ||
}; | ||
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/* CON4 */ | ||
usb@50000 { | ||
vcc-supply = <®_usb2_0_vbus>; | ||
status = "okay"; | ||
}; | ||
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/* GE0 CON1 */ | ||
ethernet@70000 { | ||
pinctrl-names = "default"; | ||
/* | ||
* The Reference Clock 0 is used to provide a | ||
* clock to the PHY | ||
*/ | ||
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; | ||
status = "okay"; | ||
phy = <&phy0>; | ||
phy-mode = "rgmii-id"; | ||
}; | ||
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mdio@72004 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&mdio_pins>; | ||
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phy0: ethernet-phy@1 { | ||
reg = <1>; | ||
}; | ||
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phy1: ethernet-phy@0 { | ||
reg = <0>; | ||
}; | ||
}; | ||
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sata@a8000 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&sata0_pins>, <&sata1_pins>; | ||
status = "okay"; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
}; | ||
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sata@e0000 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&sata2_pins>, <&sata3_pins>; | ||
status = "okay"; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
}; | ||
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sdhci@d8000 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&sdhci_pins>; | ||
cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; | ||
no-1-8-v; | ||
wp-inverted; | ||
bus-width = <8>; | ||
status = "okay"; | ||
}; | ||
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/* CON5 */ | ||
usb3@f0000 { | ||
vcc-supply = <®_usb2_1_vbus>; | ||
status = "okay"; | ||
}; | ||
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/* CON7 */ | ||
usb3@f8000 { | ||
vcc-supply = <®_usb3_vbus>; | ||
status = "okay"; | ||
}; | ||
}; | ||
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pcie-controller { | ||
status = "okay"; | ||
/* | ||
* One PCIe units is accessible through | ||
* standard PCIe slot on the board. | ||
*/ | ||
pcie@1,0 { | ||
/* Port 0, Lane 0 */ | ||
status = "okay"; | ||
}; | ||
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/* | ||
* The two other PCIe units are accessible | ||
* through mini PCIe slot on the board. | ||
*/ | ||
pcie@2,0 { | ||
/* Port 1, Lane 0 */ | ||
status = "okay"; | ||
}; | ||
pcie@3,0 { | ||
/* Port 2, Lane 0 */ | ||
status = "okay"; | ||
}; | ||
}; | ||
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gpio-fan { | ||
compatible = "gpio-fan"; | ||
gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; | ||
gpio-fan,speed-map = < 0 0 | ||
3000 1>; | ||
}; | ||
}; | ||
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reg_usb3_vbus: usb3-vbus { | ||
compatible = "regulator-fixed"; | ||
regulator-name = "usb3-vbus"; | ||
regulator-min-microvolt = <5000000>; | ||
regulator-max-microvolt = <5000000>; | ||
enable-active-high; | ||
regulator-always-on; | ||
gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; | ||
}; | ||
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reg_usb2_0_vbus: v5-vbus0 { | ||
compatible = "regulator-fixed"; | ||
regulator-name = "v5.0-vbus0"; | ||
regulator-min-microvolt = <5000000>; | ||
regulator-max-microvolt = <5000000>; | ||
enable-active-high; | ||
regulator-always-on; | ||
gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; | ||
}; | ||
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reg_usb2_1_vbus: v5-vbus1 { | ||
compatible = "regulator-fixed"; | ||
regulator-name = "v5.0-vbus1"; | ||
regulator-min-microvolt = <5000000>; | ||
regulator-max-microvolt = <5000000>; | ||
enable-active-high; | ||
regulator-always-on; | ||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; | ||
}; | ||
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reg_usb2_1_vbus: v5-vbus1 { | ||
compatible = "regulator-fixed"; | ||
regulator-name = "v5.0-vbus1"; | ||
regulator-min-microvolt = <5000000>; | ||
regulator-max-microvolt = <5000000>; | ||
enable-active-high; | ||
regulator-always-on; | ||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; | ||
}; | ||
}; | ||
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&pinctrl { | ||
pca0_pins: pca0_pins { | ||
marvell,pins = "mpp18"; | ||
marvell,function = "gpio"; | ||
}; | ||
}; |