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Merge tag 'sunxi-clk-for-5.2' of https://git.kernel.org/pub/scm/linux…
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…/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Maxime Ripard:

Our usual bunch of changes, this time, it's mainly:

 - Export a new clock for the MBUS controller on the A13
 - H6 fixes to support a finer clocking of the video and VPU engines
 - Add some Kconfig options
 - Some bit offset fixes

* tag 'sunxi-clk-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: sun5i: Export the MBUS clock
  clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk
  clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate
  clk: sunxi-ng: h6: Preset hdmi-cec clock parent
  clk: sunxi: Add Kconfig options
  clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
  clk: sunxi-ng: Allow DE clock to set parent rate
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Stephen Boyd committed Apr 19, 2019
2 parents 9e98c67 + c77ceba commit 93737fe
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Showing 10 changed files with 95 additions and 36 deletions.
1 change: 1 addition & 0 deletions drivers/clk/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -310,6 +310,7 @@ source "drivers/clk/qcom/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/samsung/Kconfig"
source "drivers/clk/sprd/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sunxi-ng/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
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3 changes: 2 additions & 1 deletion drivers/clk/sunxi-ng/ccu-sun50i-a64.c
Original file line number Diff line number Diff line change
Expand Up @@ -531,7 +531,8 @@ static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",

static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 3, BIT(31), 0);
0x104, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);

static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
static const u8 tcon0_table[] = { 0, 2, };
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19 changes: 15 additions & 4 deletions drivers/clk/sunxi-ng/ccu-sun50i-h6.c
Original file line number Diff line number Diff line change
Expand Up @@ -266,7 +266,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600,
0, 4, /* M */
24, 1, /* mux */
BIT(31), /* gate */
0);
CLK_SET_RATE_PARENT);

static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
0x60c, BIT(0), 0);
Expand Down Expand Up @@ -311,7 +311,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
0, 3, /* M */
24, 1, /* mux */
BIT(31), /* gate */
0);
CLK_SET_RATE_PARENT);

static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
0x69c, BIT(0), 0);
Expand Down Expand Up @@ -656,6 +656,8 @@ static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = {
{ .index = 1, .div = 36621 },
};

#define SUN50I_H6_HDMI_CEC_CLK_REG 0xb10
static struct ccu_mux hdmi_cec_clk = {
.enable = BIT(31),

Expand Down Expand Up @@ -689,7 +691,7 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0",
tcon_lcd0_parents, 0xb60,
24, 3, /* mux */
BIT(31), /* gate */
0);
CLK_SET_RATE_PARENT);

static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
0xb7c, BIT(0), 0);
Expand All @@ -704,7 +706,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
CLK_SET_RATE_PARENT);

static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
0xb9c, BIT(0), 0);
Expand Down Expand Up @@ -1200,6 +1202,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
val &= ~(GENMASK(21, 16) | BIT(0));
writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);

/*
* First clock parent (osc32K) is unusable for CEC. But since there
* is no good way to force parent switch (both run with same frequency),
* just set second clock parent here.
*/
val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG);
val |= BIT(24);
writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG);

return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc);
}

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4 changes: 0 additions & 4 deletions drivers/clk/sunxi-ng/ccu-sun5i.h
Original file line number Diff line number Diff line change
Expand Up @@ -60,10 +60,6 @@

/* The rest of the module clocks are exported */

#define CLK_MBUS 99

/* And finally the IEP clock */

#define CLK_NUMBER (CLK_IEP + 1)

#endif /* _CCU_SUN5I_H_ */
5 changes: 3 additions & 2 deletions drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
Original file line number Diff line number Diff line change
Expand Up @@ -513,8 +513,9 @@ static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);

static SUNXI_CCU_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x130, BIT(31), 0);

static const char * const csi_mclk_parents[] = { "pll-de", "osc24M" };
static const u8 csi_mclk_table[] = { 3, 5 };
static const char * const csi_mclk_parents[] = { "pll-video0", "pll-de",
"osc24M" };
static const u8 csi_mclk_table[] = { 0, 3, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
csi_mclk_parents, csi_mclk_table,
0x134,
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3 changes: 2 additions & 1 deletion drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
Original file line number Diff line number Diff line change
Expand Up @@ -325,7 +325,8 @@ static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram",

static const char * const de_parents[] = { "pll-video", "pll-periph0" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 2, BIT(31), 0);
0x104, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);

static const char * const tcon_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
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2 changes: 1 addition & 1 deletion drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
Original file line number Diff line number Diff line change
Expand Up @@ -240,7 +240,7 @@ static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */

static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0);
0x0cc, BIT(1), 0);

static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
0x100, BIT(0), 0);
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43 changes: 43 additions & 0 deletions drivers/clk/sunxi/Kconfig
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
menuconfig CLK_SUNXI
bool "Legacy clock support for Allwinner SoCs"
depends on ARCH_SUNXI || COMPILE_TEST
default y

if CLK_SUNXI

config CLK_SUNXI_CLOCKS
bool "Legacy clock drivers"
default y
help
Legacy clock drivers being used on older (A10, A13, A20,
A23, A31, A80) SoCs. These drivers are kept around for
Device Tree backward compatibility issues, in case one would
still use a Device Tree with one clock provider by
node. Newer Device Trees and newer SoCs use the drivers
controlled by CONFIG_SUNXI_CCU.

config CLK_SUNXI_PRCM_SUN6I
bool "Legacy A31 PRCM driver"
select MFD_SUN6I_PRCM
default y
help
Legacy clock driver for the A31 PRCM clocks. Those are
usually needed for the PMIC communication, mostly.

config CLK_SUNXI_PRCM_SUN8I
bool "Legacy sun8i PRCM driver"
select MFD_SUN6I_PRCM
default y
help
Legacy clock driver for the sun8i family PRCM clocks.
Those are usually needed for the PMIC communication,
mostly.

config CLK_SUNXI_PRCM_SUN9I
bool "Legacy A80 PRCM driver"
default y
help
Legacy clock driver for the A80 PRCM clocks. Those are
usually needed for the PMIC communication, mostly.

endif
49 changes: 27 additions & 22 deletions drivers/clk/sunxi/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -3,27 +3,32 @@
# Makefile for sunxi specific clk
#

obj-y += clk-sunxi.o clk-factors.o
obj-y += clk-a10-codec.o
obj-y += clk-a10-hosc.o
obj-y += clk-a10-mod1.o
obj-y += clk-a10-pll2.o
obj-y += clk-a10-ve.o
obj-y += clk-a20-gmac.o
obj-y += clk-mod0.o
obj-y += clk-simple-gates.o
obj-y += clk-sun4i-display.o
obj-y += clk-sun4i-pll3.o
obj-y += clk-sun4i-tcon-ch1.o
obj-y += clk-sun8i-bus-gates.o
obj-y += clk-sun8i-mbus.o
obj-y += clk-sun9i-core.o
obj-y += clk-sun9i-mmc.o
obj-y += clk-usb.o
obj-$(CONFIG_CLK_SUNXI) += clk-factors.o

obj-$(CONFIG_MACH_SUN9I) += clk-sun8i-apb0.o
obj-$(CONFIG_MACH_SUN9I) += clk-sun9i-cpus.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sunxi.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-codec.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-hosc.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-mod1.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-ve.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a20-gmac.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-mod0.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-simple-gates.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-display.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-pll3.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-tcon-ch1.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun8i-bus-gates.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun8i-mbus.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun9i-core.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun9i-mmc.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-usb.o

obj-$(CONFIG_MFD_SUN6I_PRCM) += \
clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
clk-sun8i-apb0.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun8i-apb0.o
obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun9i-cpus.o

obj-$(CONFIG_CLK_SUNXI_PRCM_SUN6I) += clk-sun6i-apb0.o
obj-$(CONFIG_CLK_SUNXI_PRCM_SUN6I) += clk-sun6i-apb0-gates.o
obj-$(CONFIG_CLK_SUNXI_PRCM_SUN6I) += clk-sun6i-ar100.o

obj-$(CONFIG_CLK_SUNXI_PRCM_SUN8I) += clk-sun8i-apb0.o
obj-$(CONFIG_CLK_SUNXI_PRCM_SUN8I) += clk-sun6i-apb0-gates.o
2 changes: 1 addition & 1 deletion include/dt-bindings/clock/sun5i-ccu.h
Original file line number Diff line number Diff line change
Expand Up @@ -100,7 +100,7 @@
#define CLK_AVS 96
#define CLK_HDMI 97
#define CLK_GPU 98

#define CLK_MBUS 99
#define CLK_IEP 100

#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */

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