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KVM: arm/arm64: vgic: Add distributor and redistributor access
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VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register offset is used to identify the
cpu for redistributor registers access.

The version of VGIC v3 specification is defined here
Documentation/virtual/kvm/devices/arm-vgic-v3.txt

Also update arch/arm/include/uapi/asm/kvm.h to compile for
AArch32 mode.

Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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Vijaya Kumar K authored and Marc Zyngier committed Jan 30, 2017
1 parent 2df903a commit 94574c9
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Showing 7 changed files with 300 additions and 36 deletions.
4 changes: 4 additions & 0 deletions arch/arm/include/uapi/asm/kvm.h
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Original file line number Diff line number Diff line change
Expand Up @@ -181,10 +181,14 @@ struct kvm_arch_memory_slot {
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0

/* KVM_IRQ_LINE irq field index values */
Expand Down
4 changes: 4 additions & 0 deletions arch/arm64/include/uapi/asm/kvm.h
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Original file line number Diff line number Diff line change
Expand Up @@ -201,10 +201,14 @@ struct kvm_arch_memory_slot {
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0

/* Device Control API on vcpu fd */
Expand Down
161 changes: 146 additions & 15 deletions virt/kvm/arm/vgic/vgic-kvm-device.c
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@
#include <kvm/arm_vgic.h>
#include <linux/uaccess.h>
#include <asm/kvm_mmu.h>
#include <asm/cputype.h>
#include "vgic.h"

/* common helpers */
Expand Down Expand Up @@ -230,14 +231,8 @@ int kvm_register_vgic_device(unsigned long type)
return ret;
}

struct vgic_reg_attr {
struct kvm_vcpu *vcpu;
gpa_t addr;
};

static int parse_vgic_v2_attr(struct kvm_device *dev,
struct kvm_device_attr *attr,
struct vgic_reg_attr *reg_attr)
int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
struct vgic_reg_attr *reg_attr)
{
int cpuid;

Expand Down Expand Up @@ -292,14 +287,14 @@ static bool lock_all_vcpus(struct kvm *kvm)
}

/**
* vgic_attr_regs_access_v2 - allows user space to access VGIC v2 state
* vgic_v2_attr_regs_access - allows user space to access VGIC v2 state
*
* @dev: kvm device handle
* @attr: kvm device attribute
* @reg: address the value is read or written
* @is_write: true if userspace is writing a register
*/
static int vgic_attr_regs_access_v2(struct kvm_device *dev,
static int vgic_v2_attr_regs_access(struct kvm_device *dev,
struct kvm_device_attr *attr,
u32 *reg, bool is_write)
{
Expand All @@ -308,7 +303,7 @@ static int vgic_attr_regs_access_v2(struct kvm_device *dev,
struct kvm_vcpu *vcpu;
int ret;

ret = parse_vgic_v2_attr(dev, attr, &reg_attr);
ret = vgic_v2_parse_attr(dev, attr, &reg_attr);
if (ret)
return ret;

Expand Down Expand Up @@ -362,7 +357,7 @@ static int vgic_v2_set_attr(struct kvm_device *dev,
if (get_user(reg, uaddr))
return -EFAULT;

return vgic_attr_regs_access_v2(dev, attr, &reg, true);
return vgic_v2_attr_regs_access(dev, attr, &reg, true);
}
}

Expand All @@ -384,7 +379,7 @@ static int vgic_v2_get_attr(struct kvm_device *dev,
u32 __user *uaddr = (u32 __user *)(long)attr->addr;
u32 reg = 0;

ret = vgic_attr_regs_access_v2(dev, attr, &reg, false);
ret = vgic_v2_attr_regs_access(dev, attr, &reg, false);
if (ret)
return ret;
return put_user(reg, uaddr);
Expand Down Expand Up @@ -428,16 +423,149 @@ struct kvm_device_ops kvm_arm_vgic_v2_ops = {
.has_attr = vgic_v2_has_attr,
};

int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
struct vgic_reg_attr *reg_attr)
{
unsigned long vgic_mpidr, mpidr_reg;

/*
* For KVM_DEV_ARM_VGIC_GRP_DIST_REGS group,
* attr might not hold MPIDR. Hence assume vcpu0.
*/
if (attr->group != KVM_DEV_ARM_VGIC_GRP_DIST_REGS) {
vgic_mpidr = (attr->attr & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) >>
KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT;

mpidr_reg = VGIC_TO_MPIDR(vgic_mpidr);
reg_attr->vcpu = kvm_mpidr_to_vcpu(dev->kvm, mpidr_reg);
} else {
reg_attr->vcpu = kvm_get_vcpu(dev->kvm, 0);
}

if (!reg_attr->vcpu)
return -EINVAL;

reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;

return 0;
}

/*
* vgic_v3_attr_regs_access - allows user space to access VGIC v3 state
*
* @dev: kvm device handle
* @attr: kvm device attribute
* @reg: address the value is read or written
* @is_write: true if userspace is writing a register
*/
static int vgic_v3_attr_regs_access(struct kvm_device *dev,
struct kvm_device_attr *attr,
u64 *reg, bool is_write)
{
struct vgic_reg_attr reg_attr;
gpa_t addr;
struct kvm_vcpu *vcpu;
int ret;
u32 tmp32;

ret = vgic_v3_parse_attr(dev, attr, &reg_attr);
if (ret)
return ret;

vcpu = reg_attr.vcpu;
addr = reg_attr.addr;

mutex_lock(&dev->kvm->lock);

if (unlikely(!vgic_initialized(dev->kvm))) {
ret = -EBUSY;
goto out;
}

if (!lock_all_vcpus(dev->kvm)) {
ret = -EBUSY;
goto out;
}

switch (attr->group) {
case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
if (is_write)
tmp32 = *reg;

ret = vgic_v3_dist_uaccess(vcpu, is_write, addr, &tmp32);
if (!is_write)
*reg = tmp32;
break;
case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
if (is_write)
tmp32 = *reg;

ret = vgic_v3_redist_uaccess(vcpu, is_write, addr, &tmp32);
if (!is_write)
*reg = tmp32;
break;
default:
ret = -EINVAL;
break;
}

unlock_all_vcpus(dev->kvm);
out:
mutex_unlock(&dev->kvm->lock);
return ret;
}

static int vgic_v3_set_attr(struct kvm_device *dev,
struct kvm_device_attr *attr)
{
return vgic_set_common_attr(dev, attr);
int ret;

ret = vgic_set_common_attr(dev, attr);
if (ret != -ENXIO)
return ret;

switch (attr->group) {
case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
u32 __user *uaddr = (u32 __user *)(long)attr->addr;
u32 tmp32;
u64 reg;

if (get_user(tmp32, uaddr))
return -EFAULT;

reg = tmp32;
return vgic_v3_attr_regs_access(dev, attr, &reg, true);
}
}
return -ENXIO;
}

static int vgic_v3_get_attr(struct kvm_device *dev,
struct kvm_device_attr *attr)
{
return vgic_get_common_attr(dev, attr);
int ret;

ret = vgic_get_common_attr(dev, attr);
if (ret != -ENXIO)
return ret;

switch (attr->group) {
case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
u32 __user *uaddr = (u32 __user *)(long)attr->addr;
u64 reg;
u32 tmp32;

ret = vgic_v3_attr_regs_access(dev, attr, &reg, false);
if (ret)
return ret;
tmp32 = reg;
return put_user(tmp32, uaddr);
}
}

return -ENXIO;
}

static int vgic_v3_has_attr(struct kvm_device *dev,
Expand All @@ -451,6 +579,9 @@ static int vgic_v3_has_attr(struct kvm_device *dev,
return 0;
}
break;
case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
return vgic_v3_has_attr_regs(dev, attr);
case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
return 0;
case KVM_DEV_ARM_VGIC_GRP_CTRL:
Expand Down
40 changes: 21 additions & 19 deletions virt/kvm/arm/vgic/vgic-mmio-v2.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -369,21 +369,30 @@ unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)

int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
{
int nr_irqs = dev->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
const struct vgic_register_region *regions;
const struct vgic_register_region *region;
struct vgic_io_device iodev;
struct vgic_reg_attr reg_attr;
struct kvm_vcpu *vcpu;
gpa_t addr;
int nr_regions, i, len;
int ret;

ret = vgic_v2_parse_attr(dev, attr, &reg_attr);
if (ret)
return ret;

addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
vcpu = reg_attr.vcpu;
addr = reg_attr.addr;

switch (attr->group) {
case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
regions = vgic_v2_dist_registers;
nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
iodev.regions = vgic_v2_dist_registers;
iodev.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
iodev.base_addr = 0;
break;
case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
regions = vgic_v2_cpu_registers;
nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
iodev.regions = vgic_v2_cpu_registers;
iodev.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
iodev.base_addr = 0;
break;
default:
return -ENXIO;
Expand All @@ -393,18 +402,11 @@ int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
if (addr & 3)
return -ENXIO;

for (i = 0; i < nr_regions; i++) {
if (regions[i].bits_per_irq)
len = (regions[i].bits_per_irq * nr_irqs) / 8;
else
len = regions[i].len;

if (regions[i].reg_offset <= addr &&
regions[i].reg_offset + len > addr)
return 0;
}
region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
if (!region)
return -ENXIO;

return -ENXIO;
return 0;
}

int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
Expand Down
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