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ice: process 1588 PTP capabilities during initialization
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The device firmware reports PTP clock capabilities to each PF during
initialization. This includes various information for both the overall
device and the individual function, including

For functions:
* whether this function has timesync enabled
* whether this function owns one of the 2 possible clock timers, and
  which one
* which timer the function is associated with
* the clock frequency, if the device supports multiple clock frequencies
* The GPIO pin association for the timer owned by this PF, if any

For the device:
* Which PF owns timer 0, if any
* Which PF owns timer 1, if any
* whether timer 0 is enabled
* whether timer 1 is enabled

Extract the bits from the capabilities information reported by firmware
and store them in the device and function capability structures.o

This information will be used in a future change to have the function
driver enable PTP hardware clock support.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Tested-by: Tony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
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Jacob Keller authored and Tony Nguyen committed Jun 11, 2021
1 parent 8f5ee3c commit 9733cc9
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Showing 3 changed files with 151 additions and 0 deletions.
1 change: 1 addition & 0 deletions drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
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Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,7 @@ struct ice_aqc_list_caps_elem {
#define ICE_AQC_CAPS_TXQS 0x0042
#define ICE_AQC_CAPS_MSIX 0x0043
#define ICE_AQC_CAPS_FD 0x0045
#define ICE_AQC_CAPS_1588 0x0046
#define ICE_AQC_CAPS_MAX_MTU 0x0047
#define ICE_AQC_CAPS_NVM_VER 0x0048
#define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049
Expand Down
99 changes: 99 additions & 0 deletions drivers/net/ethernet/intel/ice/ice_common.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2092,6 +2092,48 @@ ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
func_p->guar_num_vsi);
}

/**
* ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
* @hw: pointer to the HW struct
* @func_p: pointer to function capabilities structure
* @cap: pointer to the capability element to parse
*
* Extract function capabilities for ICE_AQC_CAPS_1588.
*/
static void
ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
struct ice_aqc_list_caps_elem *cap)
{
struct ice_ts_func_info *info = &func_p->ts_func_info;
u32 number = le32_to_cpu(cap->number);

info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
func_p->common_cap.ieee_1588 = info->ena;

info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);

info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;
info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);

ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
func_p->common_cap.ieee_1588);
ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
info->src_tmr_owned);
ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
info->tmr_ena);
ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
info->tmr_index_owned);
ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
info->tmr_index_assoc);
ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
info->clk_freq);
ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
info->clk_src);
}

/**
* ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
* @hw: pointer to the HW struct
Expand Down Expand Up @@ -2158,6 +2200,9 @@ ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
case ICE_AQC_CAPS_VSI:
ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
break;
case ICE_AQC_CAPS_1588:
ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);
break;
case ICE_AQC_CAPS_FD:
ice_parse_fdir_func_caps(hw, func_p);
break;
Expand Down Expand Up @@ -2230,6 +2275,57 @@ ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
dev_p->num_vsi_allocd_to_host);
}

/**
* ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
* @hw: pointer to the HW struct
* @dev_p: pointer to device capabilities structure
* @cap: capability element to parse
*
* Parse ICE_AQC_CAPS_1588 for device capabilities.
*/
static void
ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
struct ice_aqc_list_caps_elem *cap)
{
struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
u32 logical_id = le32_to_cpu(cap->logical_id);
u32 phys_id = le32_to_cpu(cap->phys_id);
u32 number = le32_to_cpu(cap->number);

info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
dev_p->common_cap.ieee_1588 = info->ena;

info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);

info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S;
info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);

info->ena_ports = logical_id;
info->tmr_own_map = phys_id;

ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
dev_p->common_cap.ieee_1588);
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
info->tmr0_owner);
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
info->tmr0_owned);
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
info->tmr0_ena);
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
info->tmr1_owner);
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
info->tmr1_owned);
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
info->tmr1_ena);
ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
info->ena_ports);
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
info->tmr_own_map);
}

/**
* ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
* @hw: pointer to the HW struct
Expand Down Expand Up @@ -2291,6 +2387,9 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
case ICE_AQC_CAPS_VSI:
ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
break;
case ICE_AQC_CAPS_1588:
ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);
break;
case ICE_AQC_CAPS_FD:
ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
break;
Expand Down
51 changes: 51 additions & 0 deletions drivers/net/ethernet/intel/ice/ice_type.h
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Original file line number Diff line number Diff line change
Expand Up @@ -265,6 +265,7 @@ struct ice_hw_common_caps {
u8 rss_table_entry_width; /* RSS Entry width in bits */

u8 dcb;
u8 ieee_1588;
u8 rdma;

bool nvm_update_pending_nvm;
Expand All @@ -277,6 +278,54 @@ struct ice_hw_common_caps {
#define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
};

/* IEEE 1588 TIME_SYNC specific info */
/* Function specific definitions */
#define ICE_TS_FUNC_ENA_M BIT(0)
#define ICE_TS_SRC_TMR_OWND_M BIT(1)
#define ICE_TS_TMR_ENA_M BIT(2)
#define ICE_TS_TMR_IDX_OWND_S 4
#define ICE_TS_TMR_IDX_OWND_M BIT(4)
#define ICE_TS_CLK_FREQ_S 16
#define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
#define ICE_TS_CLK_SRC_S 20
#define ICE_TS_CLK_SRC_M BIT(20)
#define ICE_TS_TMR_IDX_ASSOC_S 24
#define ICE_TS_TMR_IDX_ASSOC_M BIT(24)

struct ice_ts_func_info {
/* Function specific info */
u32 clk_freq;
u8 clk_src;
u8 tmr_index_assoc;
u8 ena;
u8 tmr_index_owned;
u8 src_tmr_owned;
u8 tmr_ena;
};

/* Device specific definitions */
#define ICE_TS_TMR0_OWNR_M 0x7
#define ICE_TS_TMR0_OWND_M BIT(3)
#define ICE_TS_TMR1_OWNR_S 4
#define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
#define ICE_TS_TMR1_OWND_M BIT(7)
#define ICE_TS_DEV_ENA_M BIT(24)
#define ICE_TS_TMR0_ENA_M BIT(25)
#define ICE_TS_TMR1_ENA_M BIT(26)

struct ice_ts_dev_info {
/* Device specific info */
u32 ena_ports;
u32 tmr_own_map;
u32 tmr0_owner;
u32 tmr1_owner;
u8 tmr0_owned;
u8 tmr1_owned;
u8 ena;
u8 tmr0_ena;
u8 tmr1_ena;
};

/* Function specific capabilities */
struct ice_hw_func_caps {
struct ice_hw_common_caps common_cap;
Expand All @@ -285,6 +334,7 @@ struct ice_hw_func_caps {
u32 guar_num_vsi;
u32 fd_fltr_guar; /* Number of filters guaranteed */
u32 fd_fltr_best_effort; /* Number of best effort filters */
struct ice_ts_func_info ts_func_info;
};

/* Device wide capabilities */
Expand All @@ -293,6 +343,7 @@ struct ice_hw_dev_caps {
u32 num_vfs_exposed; /* Total number of VFs exposed */
u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
u32 num_flow_director_fltr; /* Number of FD filters available */
struct ice_ts_dev_info ts_dev_info;
u32 num_funcs;
};

Expand Down

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