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ARM: 6794/1: SPEAr: Append UL to device address macros.
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Reviewed-by: Stanley Miao <stanley.miao@windriver.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Shiraz Hashim authored and Russell King committed Mar 9, 2011
1 parent 8fc4ef4 commit 981a95d
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Showing 5 changed files with 126 additions and 123 deletions.
71 changes: 36 additions & 35 deletions arch/arm/mach-spear3xx/include/mach/spear.h
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#ifndef __MACH_SPEAR3XX_H
#define __MACH_SPEAR3XX_H

#include <asm/memory.h>
#include <mach/spear300.h>
#include <mach/spear310.h>
#include <mach/spear320.h>

#define SPEAR3XX_ML_SDRAM_BASE 0x00000000
#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)

#define SPEAR3XX_ICM9_BASE 0xC0000000
#define SPEAR3XX_ICM9_BASE UL(0xC0000000)

/* ICM1 - Low speed connection */
#define SPEAR3XX_ICM1_2_BASE 0xD0000000
#define SPEAR3XX_ICM1_UART_BASE 0xD0000000
#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000
#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000
#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000
#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000
#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000
#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000
#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)

/* ICM2 - Application Subsystem */
#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000
#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000
#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)

/* ICM4 - High Speed Connection */
#define SPEAR3XX_ICM4_BASE 0xE0000000
#define SPEAR3XX_ICM4_MII_BASE 0xE0800000
#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000
#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000
#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000
#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000
#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000
#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000
#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000
#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)

/* ML1 - Multi Layer CPU Subsystem */
#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000
#define SPEAR3XX_ML1_TMR_BASE 0xF0000000
#define SPEAR3XX_ML1_VIC_BASE 0xF1100000
#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)

/* ICM3 - Basic Subsystem */
#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000
#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000
#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000
#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000
#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000
#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000
#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000
#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000
#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000
#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000
#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)

/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
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30 changes: 15 additions & 15 deletions arch/arm/mach-spear3xx/include/mach/spear300.h
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#define __MACH_SPEAR300_H

/* Base address of various IPs */
#define SPEAR300_TELECOM_BASE 0x50000000
#define SPEAR300_TELECOM_BASE UL(0x50000000)

/* Interrupt registers offsets and masks */
#define INT_ENB_MASK_REG 0x54
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#define SHIRQ_RAS1_MASK 0x1FF

#define SPEAR300_CLCD_BASE 0x60000000
#define SPEAR300_SDHCI_BASE 0x70000000
#define SPEAR300_NAND_0_BASE 0x80000000
#define SPEAR300_NAND_1_BASE 0x84000000
#define SPEAR300_NAND_2_BASE 0x88000000
#define SPEAR300_NAND_3_BASE 0x8c000000
#define SPEAR300_NOR_0_BASE 0x90000000
#define SPEAR300_NOR_1_BASE 0x91000000
#define SPEAR300_NOR_2_BASE 0x92000000
#define SPEAR300_NOR_3_BASE 0x93000000
#define SPEAR300_FSMC_BASE 0x94000000
#define SPEAR300_SOC_CONFIG_BASE 0x99000000
#define SPEAR300_KEYBOARD_BASE 0xA0000000
#define SPEAR300_GPIO_BASE 0xA9000000
#define SPEAR300_CLCD_BASE UL(0x60000000)
#define SPEAR300_SDHCI_BASE UL(0x70000000)
#define SPEAR300_NAND_0_BASE UL(0x80000000)
#define SPEAR300_NAND_1_BASE UL(0x84000000)
#define SPEAR300_NAND_2_BASE UL(0x88000000)
#define SPEAR300_NAND_3_BASE UL(0x8c000000)
#define SPEAR300_NOR_0_BASE UL(0x90000000)
#define SPEAR300_NOR_1_BASE UL(0x91000000)
#define SPEAR300_NOR_2_BASE UL(0x92000000)
#define SPEAR300_NOR_3_BASE UL(0x93000000)
#define SPEAR300_FSMC_BASE UL(0x94000000)
#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
#define SPEAR300_GPIO_BASE UL(0xA9000000)

#endif /* __MACH_SPEAR300_H */

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22 changes: 11 additions & 11 deletions arch/arm/mach-spear3xx/include/mach/spear310.h
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#ifndef __MACH_SPEAR310_H
#define __MACH_SPEAR310_H

#define SPEAR310_NAND_BASE 0x40000000
#define SPEAR310_FSMC_BASE 0x44000000
#define SPEAR310_UART1_BASE 0xB2000000
#define SPEAR310_UART2_BASE 0xB2080000
#define SPEAR310_UART3_BASE 0xB2100000
#define SPEAR310_UART4_BASE 0xB2180000
#define SPEAR310_UART5_BASE 0xB2200000
#define SPEAR310_HDLC_BASE 0xB2800000
#define SPEAR310_RS485_0_BASE 0xB3000000
#define SPEAR310_RS485_1_BASE 0xB3800000
#define SPEAR310_SOC_CONFIG_BASE 0xB4000000
#define SPEAR310_NAND_BASE UL(0x40000000)
#define SPEAR310_FSMC_BASE UL(0x44000000)
#define SPEAR310_UART1_BASE UL(0xB2000000)
#define SPEAR310_UART2_BASE UL(0xB2080000)
#define SPEAR310_UART3_BASE UL(0xB2100000)
#define SPEAR310_UART4_BASE UL(0xB2180000)
#define SPEAR310_UART5_BASE UL(0xB2200000)
#define SPEAR310_HDLC_BASE UL(0xB2800000)
#define SPEAR310_RS485_0_BASE UL(0xB3000000)
#define SPEAR310_RS485_1_BASE UL(0xB3800000)
#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)

/* Interrupt registers offsets and masks */
#define INT_STS_MASK_REG 0x04
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35 changes: 18 additions & 17 deletions arch/arm/mach-spear3xx/include/mach/spear320.h
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Expand Up @@ -16,23 +16,24 @@
#ifndef __MACH_SPEAR320_H
#define __MACH_SPEAR320_H

#define SPEAR320_EMI_CTRL_BASE 0x40000000
#define SPEAR320_FSMC_BASE 0x4C000000
#define SPEAR320_I2S_BASE 0x60000000
#define SPEAR320_SDHCI_BASE 0x70000000
#define SPEAR320_CLCD_BASE 0x90000000
#define SPEAR320_PAR_PORT_BASE 0xA0000000
#define SPEAR320_CAN0_BASE 0xA1000000
#define SPEAR320_CAN1_BASE 0xA2000000
#define SPEAR320_UART1_BASE 0xA3000000
#define SPEAR320_UART2_BASE 0xA4000000
#define SPEAR320_SSP0_BASE 0xA5000000
#define SPEAR320_SSP1_BASE 0xA6000000
#define SPEAR320_I2C_BASE 0xA7000000
#define SPEAR320_PWM_BASE 0xA8000000
#define SPEAR320_SMII0_BASE 0xAA000000
#define SPEAR320_SMII1_BASE 0xAB000000
#define SPEAR320_SOC_CONFIG_BASE 0xB3000000
#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
#define SPEAR320_FSMC_BASE UL(0x4C000000)
#define SPEAR320_NAND_BASE UL(0x50000000)
#define SPEAR320_I2S_BASE UL(0x60000000)
#define SPEAR320_SDHCI_BASE UL(0x70000000)
#define SPEAR320_CLCD_BASE UL(0x90000000)
#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
#define SPEAR320_CAN0_BASE UL(0xA1000000)
#define SPEAR320_CAN1_BASE UL(0xA2000000)
#define SPEAR320_UART1_BASE UL(0xA3000000)
#define SPEAR320_UART2_BASE UL(0xA4000000)
#define SPEAR320_SSP0_BASE UL(0xA5000000)
#define SPEAR320_SSP1_BASE UL(0xA6000000)
#define SPEAR320_I2C_BASE UL(0xA7000000)
#define SPEAR320_PWM_BASE UL(0xA8000000)
#define SPEAR320_SMII0_BASE UL(0xAA000000)
#define SPEAR320_SMII1_BASE UL(0xAB000000)
#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)

/* Interrupt registers offsets and masks */
#define INT_STS_MASK_REG 0x04
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91 changes: 46 additions & 45 deletions arch/arm/mach-spear6xx/include/mach/spear.h
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Expand Up @@ -14,69 +14,70 @@
#ifndef __MACH_SPEAR6XX_H
#define __MACH_SPEAR6XX_H

#include <asm/memory.h>
#include <mach/spear600.h>

#define SPEAR6XX_ML_SDRAM_BASE 0x00000000
#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
/* ICM1 - Low speed connection */
#define SPEAR6XX_ICM1_BASE 0xD0000000
#define SPEAR6XX_ICM1_BASE UL(0xD0000000)

#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000
#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)

#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000
#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000
#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000
#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000
#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000
#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000
#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000
#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000
#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000
#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)

/* ICM2 - Application Subsystem */
#define SPEAR6XX_ICM2_BASE 0xD8000000
#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000
#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000
#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000
#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000
#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000
#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)

/* ML-1, 2 - Multi Layer CPU Subsystem */
#define SPEAR6XX_ML_CPU_BASE 0xF0000000
#define SPEAR6XX_CPU_TMR_BASE 0xF0000000
#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000
#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000
#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000)
#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000
#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)

/* ICM3 - Basic Subsystem */
#define SPEAR6XX_ICM3_BASE 0xF8000000
#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000
#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000
#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000
#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000
#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000
#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000
#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000
#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000
#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000
#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000)
#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000
#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)

/* ICM4 - High Speed Connection */
#define SPEAR6XX_ICM4_BASE 0xE0000000
#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000
#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000
#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000
#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000
#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000
#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000
#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000
#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000
#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000
#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)

/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
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