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Adds pci/pci-xlr.c to support for XLR PCI/PCI-X interface and XLS PCIe interface. Update irq.c to ack PCI interrupts, use irq handler data to do the PCI/PCIe bus ack. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2337/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Jayachandran C
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May 19, 2011
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| /* | ||
| * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | ||
| * reserved. | ||
| * | ||
| * This software is available to you under a choice of one of two | ||
| * licenses. You may choose to be licensed under the terms of the GNU | ||
| * General Public License (GPL) Version 2, available from the file | ||
| * COPYING in the main directory of this source tree, or the NetLogic | ||
| * license below: | ||
| * | ||
| * Redistribution and use in source and binary forms, with or without | ||
| * modification, are permitted provided that the following conditions | ||
| * are met: | ||
| * | ||
| * 1. Redistributions of source code must retain the above copyright | ||
| * notice, this list of conditions and the following disclaimer. | ||
| * 2. Redistributions in binary form must reproduce the above copyright | ||
| * notice, this list of conditions and the following disclaimer in | ||
| * the documentation and/or other materials provided with the | ||
| * distribution. | ||
| * | ||
| * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | ||
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
| * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
| * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | ||
| * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
| * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
| * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
| * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
| * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
| * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
| * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| */ | ||
|
|
||
| #include <linux/types.h> | ||
| #include <linux/pci.h> | ||
| #include <linux/kernel.h> | ||
| #include <linux/init.h> | ||
| #include <linux/mm.h> | ||
| #include <linux/console.h> | ||
|
|
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| #include <asm/io.h> | ||
|
|
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| #include <asm/netlogic/interrupt.h> | ||
| #include <asm/netlogic/xlr/iomap.h> | ||
| #include <asm/netlogic/xlr/pic.h> | ||
| #include <asm/netlogic/xlr/xlr.h> | ||
|
|
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| static void *pci_config_base; | ||
|
|
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| #define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off)) | ||
|
|
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| /* PCI ops */ | ||
| static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, | ||
| int where) | ||
| { | ||
| u32 data; | ||
| u32 *cfgaddr; | ||
|
|
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| cfgaddr = (u32 *)(pci_config_base + | ||
| pci_cfg_addr(bus->number, devfn, where & ~3)); | ||
| data = *cfgaddr; | ||
| return cpu_to_le32(data); | ||
| } | ||
|
|
||
| static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, | ||
| int where, u32 data) | ||
| { | ||
| u32 *cfgaddr; | ||
|
|
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| cfgaddr = (u32 *)(pci_config_base + | ||
| pci_cfg_addr(bus->number, devfn, where & ~3)); | ||
| *cfgaddr = cpu_to_le32(data); | ||
| } | ||
|
|
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| static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, | ||
| int where, int size, u32 *val) | ||
| { | ||
| u32 data; | ||
|
|
||
| if ((size == 2) && (where & 1)) | ||
| return PCIBIOS_BAD_REGISTER_NUMBER; | ||
| else if ((size == 4) && (where & 3)) | ||
| return PCIBIOS_BAD_REGISTER_NUMBER; | ||
|
|
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| data = pci_cfg_read_32bit(bus, devfn, where); | ||
|
|
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| if (size == 1) | ||
| *val = (data >> ((where & 3) << 3)) & 0xff; | ||
| else if (size == 2) | ||
| *val = (data >> ((where & 3) << 3)) & 0xffff; | ||
| else | ||
| *val = data; | ||
|
|
||
| return PCIBIOS_SUCCESSFUL; | ||
| } | ||
|
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|
|
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| static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, | ||
| int where, int size, u32 val) | ||
| { | ||
| u32 data; | ||
|
|
||
| if ((size == 2) && (where & 1)) | ||
| return PCIBIOS_BAD_REGISTER_NUMBER; | ||
| else if ((size == 4) && (where & 3)) | ||
| return PCIBIOS_BAD_REGISTER_NUMBER; | ||
|
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| data = pci_cfg_read_32bit(bus, devfn, where); | ||
|
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| if (size == 1) | ||
| data = (data & ~(0xff << ((where & 3) << 3))) | | ||
| (val << ((where & 3) << 3)); | ||
| else if (size == 2) | ||
| data = (data & ~(0xffff << ((where & 3) << 3))) | | ||
| (val << ((where & 3) << 3)); | ||
| else | ||
| data = val; | ||
|
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| pci_cfg_write_32bit(bus, devfn, where, data); | ||
|
|
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| return PCIBIOS_SUCCESSFUL; | ||
| } | ||
|
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| struct pci_ops nlm_pci_ops = { | ||
| .read = nlm_pcibios_read, | ||
| .write = nlm_pcibios_write | ||
| }; | ||
|
|
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| static struct resource nlm_pci_mem_resource = { | ||
| .name = "XLR PCI MEM", | ||
| .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ | ||
| .end = 0xdfffffffUL, | ||
| .flags = IORESOURCE_MEM, | ||
| }; | ||
|
|
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| static struct resource nlm_pci_io_resource = { | ||
| .name = "XLR IO MEM", | ||
| .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */ | ||
| .end = 0x100fffffUL, | ||
| .flags = IORESOURCE_IO, | ||
| }; | ||
|
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| struct pci_controller nlm_pci_controller = { | ||
| .index = 0, | ||
| .pci_ops = &nlm_pci_ops, | ||
| .mem_resource = &nlm_pci_mem_resource, | ||
| .mem_offset = 0x00000000UL, | ||
| .io_resource = &nlm_pci_io_resource, | ||
| .io_offset = 0x00000000UL, | ||
| }; | ||
|
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| int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | ||
| { | ||
| if (!nlm_chip_is_xls()) | ||
| return PIC_PCIX_IRQ; /* for XLR just one IRQ*/ | ||
|
|
||
| /* | ||
| * For XLS PCIe, there is an IRQ per Link, find out which | ||
| * link the device is on to assign interrupts | ||
| */ | ||
| if (dev->bus->self == NULL) | ||
| return 0; | ||
|
|
||
| switch (dev->bus->self->devfn) { | ||
| case 0x0: | ||
| return PIC_PCIE_LINK0_IRQ; | ||
| case 0x8: | ||
| return PIC_PCIE_LINK1_IRQ; | ||
| case 0x10: | ||
| if (nlm_chip_is_xls_b()) | ||
| return PIC_PCIE_XLSB0_LINK2_IRQ; | ||
| else | ||
| return PIC_PCIE_LINK2_IRQ; | ||
| case 0x18: | ||
| if (nlm_chip_is_xls_b()) | ||
| return PIC_PCIE_XLSB0_LINK3_IRQ; | ||
| else | ||
| return PIC_PCIE_LINK3_IRQ; | ||
| } | ||
| WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); | ||
| return 0; | ||
| } | ||
|
|
||
| /* Do platform specific device initialization at pci_enable_device() time */ | ||
| int pcibios_plat_dev_init(struct pci_dev *dev) | ||
| { | ||
| return 0; | ||
| } | ||
|
|
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| static int __init pcibios_init(void) | ||
| { | ||
| /* PSB assigns PCI resources */ | ||
| pci_probe_only = 1; | ||
| pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); | ||
|
|
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| /* Extend IO port for memory mapped io */ | ||
| ioport_resource.start = 0; | ||
| ioport_resource.end = ~0; | ||
|
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| set_io_port_base(CKSEG1); | ||
| nlm_pci_controller.io_map_base = CKSEG1; | ||
|
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| pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n"); | ||
| register_pci_controller(&nlm_pci_controller); | ||
|
|
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| return 0; | ||
| } | ||
|
|
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| arch_initcall(pcibios_init); | ||
|
|
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| struct pci_fixup pcibios_fixups[] = { | ||
| {0} | ||
| }; |