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powerpc: Remove use of CONFIG_PPC_MERGE
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Now that arch/ppc is gone and CONFIG_PPC_MERGE is always set, remove
the dead code associated with !CONFIG_PPC_MERGE from arch/powerpc
and include/asm-powerpc.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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Kumar Gala authored and Paul Mackerras committed Aug 4, 2008
1 parent c7c8eed commit 9c4cb82
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Showing 15 changed files with 6 additions and 368 deletions.
2 changes: 1 addition & 1 deletion arch/powerpc/Kconfig.debug
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Expand Up @@ -97,7 +97,7 @@ config IRQSTACKS

config VIRQ_DEBUG
bool "Expose hardware/virtual IRQ mapping via debugfs"
depends on DEBUG_FS && PPC_MERGE
depends on DEBUG_FS
help
This option will show the mapping relationship between hardware irq
numbers and virtual irq numbers. The mapping is exposed via debugfs
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6 changes: 1 addition & 5 deletions arch/powerpc/include/asm/dcr.h
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Expand Up @@ -65,17 +65,13 @@ typedef dcr_host_mmio_t dcr_host_t;
#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */

/*
* On CONFIG_PPC_MERGE, we have additional helpers to read the DCR
* base from the device-tree
* additional helpers to read the DCR * base from the device-tree
*/
#ifdef CONFIG_PPC_MERGE
struct device_node;
extern unsigned int dcr_resource_start(struct device_node *np,
unsigned int index);
extern unsigned int dcr_resource_len(struct device_node *np,
unsigned int index);
#endif /* CONFIG_PPC_MERGE */

#endif /* CONFIG_PPC_DCR */
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
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5 changes: 0 additions & 5 deletions arch/powerpc/include/asm/i8259.h
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Expand Up @@ -4,14 +4,9 @@

#include <linux/irq.h>

#ifdef CONFIG_PPC_MERGE
extern void i8259_init(struct device_node *node, unsigned long intack_addr);
extern unsigned int i8259_irq(void);
extern struct irq_host *i8259_get_host(void);
#else
extern void i8259_init(unsigned long intack_addr, int offset);
extern int i8259_irq(void);
#endif

#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_I8259_H */
7 changes: 0 additions & 7 deletions arch/powerpc/include/asm/ipic.h
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Expand Up @@ -77,15 +77,8 @@ extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
extern u32 ipic_get_mcp_status(void);
extern void ipic_clear_mcp_status(u32 mask);

#ifdef CONFIG_PPC_MERGE
extern struct ipic * ipic_init(struct device_node *node, unsigned int flags);
extern unsigned int ipic_get_irq(void);
#else
extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
unsigned int irq_offset,
unsigned char *senses, unsigned int senses_count);
extern int ipic_get_irq(void);
#endif

#endif /* __ASM_IPIC_H__ */
#endif /* __KERNEL__ */
288 changes: 0 additions & 288 deletions arch/powerpc/include/asm/irq.h
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Expand Up @@ -25,8 +25,6 @@

extern atomic_t ppc_n_lost_interrupts;

#ifdef CONFIG_PPC_MERGE

/* This number is used when no interrupt has been assigned */
#define NO_IRQ (0)

Expand Down Expand Up @@ -326,292 +324,6 @@ static __inline__ int irq_canonicalize(int irq)
return irq;
}


#else /* CONFIG_PPC_MERGE */

/* This number is used when no interrupt has been assigned */
#define NO_IRQ (-1)
#define NO_IRQ_IGNORE (-2)


/*
* These constants are used for passing information about interrupt
* signal polarity and level/edge sensing to the low-level PIC chip
* drivers.
*/
#define IRQ_SENSE_MASK 0x1
#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */

#define IRQ_POLARITY_MASK 0x2
#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */


#if defined(CONFIG_40x)
#include <asm/ibm4xx.h>

#ifndef NR_BOARD_IRQS
#define NR_BOARD_IRQS 0
#endif

#ifndef UIC_WIDTH /* Number of interrupts per device */
#define UIC_WIDTH 32
#endif

#ifndef NR_UICS /* number of UIC devices */
#define NR_UICS 1
#endif

#if defined (CONFIG_403)
/*
* The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
* 32 possible interrupts, a majority of which are not implemented on
* all cores. There are six configurable, external interrupt pins and
* there are eight internal interrupts for the on-chip serial port
* (SPU), DMA controller, and JTAG controller.
*
*/

#define NR_AIC_IRQS 32
#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)

#elif !defined (CONFIG_403)

/*
* The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
* possible interrupts as well. There are seven, configurable external
* interrupt pins and there are 17 internal interrupts for the on-chip
* serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
*
*/


#define NR_UIC_IRQS UIC_WIDTH
#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
#endif

#elif defined(CONFIG_44x)
#include <asm/ibm44x.h>

#define NR_UIC_IRQS 32
#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)

#elif defined(CONFIG_8xx)

/* Now include the board configuration specific associations.
*/
#include <asm/mpc8xx.h>

/* The MPC8xx cores have 16 possible interrupts. There are eight
* possible level sensitive interrupts assigned and generated internally
* from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
* There are eight external interrupts (IRQs) that can be configured
* as either level or edge sensitive.
*
* On some implementations, there is also the possibility of an 8259
* through the PCI and PCI-ISA bridges.
*
* We are "flattening" the interrupt vectors of the cascaded CPM
* and 8259 interrupt controllers so that we can uniquely identify
* any interrupt source with a single integer.
*/
#define NR_SIU_INTS 16
#define NR_CPM_INTS 32
#ifndef NR_8259_INTS
#define NR_8259_INTS 0
#endif

#define SIU_IRQ_OFFSET 0
#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)

#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)

/* These values must be zero-based and map 1:1 with the SIU configuration.
* They are used throughout the 8xx I/O subsystem to generate
* interrupt masks, flags, and other control patterns. This is why the
* current kernel assumption of the 8259 as the base controller is such
* a pain in the butt.
*/
#define SIU_IRQ0 (0) /* Highest priority */
#define SIU_LEVEL0 (1)
#define SIU_IRQ1 (2)
#define SIU_LEVEL1 (3)
#define SIU_IRQ2 (4)
#define SIU_LEVEL2 (5)
#define SIU_IRQ3 (6)
#define SIU_LEVEL3 (7)
#define SIU_IRQ4 (8)
#define SIU_LEVEL4 (9)
#define SIU_IRQ5 (10)
#define SIU_LEVEL5 (11)
#define SIU_IRQ6 (12)
#define SIU_LEVEL6 (13)
#define SIU_IRQ7 (14)
#define SIU_LEVEL7 (15)

#define MPC8xx_INT_FEC1 SIU_LEVEL1
#define MPC8xx_INT_FEC2 SIU_LEVEL3

#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)

/* The internal interrupts we can configure as we see fit.
* My personal preference is CPM at level 2, which puts it above the
* MBX PCI/ISA/IDE interrupts.
*/
#ifndef PIT_INTERRUPT
#define PIT_INTERRUPT SIU_LEVEL0
#endif
#ifndef CPM_INTERRUPT
#define CPM_INTERRUPT SIU_LEVEL2
#endif
#ifndef PCMCIA_INTERRUPT
#define PCMCIA_INTERRUPT SIU_LEVEL6
#endif
#ifndef DEC_INTERRUPT
#define DEC_INTERRUPT SIU_LEVEL7
#endif

/* Some internal interrupt registers use an 8-bit mask for the interrupt
* level instead of a number.
*/
#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))

#else /* CONFIG_40x + CONFIG_8xx */
/*
* this is the # irq's for all ppc arch's (pmac/chrp/prep)
* so it is the max of them all
*/
#define NR_IRQS 256
#define __DO_IRQ_CANON 1

#ifndef CONFIG_8260

#define NUM_8259_INTERRUPTS 16

#else /* CONFIG_8260 */

/* The 8260 has an internal interrupt controller with a maximum of
* 64 IRQs. We will use NR_IRQs from above since it is large enough.
* Don't be confused by the 8260 documentation where they list an
* "interrupt number" and "interrupt vector". We are only interested
* in the interrupt vector. There are "reserved" holes where the
* vector number increases, but the interrupt number in the table does not.
* (Document errata updates have fixed this...make sure you have up to
* date processor documentation -- Dan).
*/

#ifndef CPM_IRQ_OFFSET
#define CPM_IRQ_OFFSET 0
#endif

#define NR_CPM_INTS 64

#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
#define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET)
#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
#define SIU_INT_PCI ((uint)0x12 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)

#endif /* CONFIG_8260 */

#endif /* Whatever way too big #ifdef */

#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
/* pedantic: these are long because they are used with set_bit --RR */
extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];

/*
* Because many systems have two overlapping names spaces for
* interrupts (ISA and XICS for example), and the ISA interrupts
* have historically not been easy to renumber, we allow ISA
* interrupts to take values 0 - 15, and shift up the remaining
* interrupts by 0x10.
*/
#define NUM_ISA_INTERRUPTS 0x10
extern int __irq_offset_value;

static inline int irq_offset_up(int irq)
{
return(irq + __irq_offset_value);
}

static inline int irq_offset_down(int irq)
{
return(irq - __irq_offset_value);
}

static inline int irq_offset_value(void)
{
return __irq_offset_value;
}

#ifdef __DO_IRQ_CANON
extern int ppc_do_canonicalize_irqs;
#else
#define ppc_do_canonicalize_irqs 0
#endif

static __inline__ int irq_canonicalize(int irq)
{
if (ppc_do_canonicalize_irqs && irq == 2)
irq = 9;
return irq;
}
#endif /* CONFIG_PPC_MERGE */

extern int distribute_irqs;

struct irqaction;
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