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amd/amdgpu: Enable debug vmid trap mask
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To always have wave state info available for the debugger, we enable
the debug trap mask always for vg10 asics.

Change-Id: Ic8d50c39ecbc70b031f8c199c1bcae78674a4edf
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
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Philip Cox authored and changzhu committed Jul 24, 2019
1 parent 86778e8 commit 9dd512a
Showing 2 changed files with 11 additions and 9 deletions.
9 changes: 0 additions & 9 deletions drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
Original file line number Diff line number Diff line change
@@ -870,13 +870,6 @@ static uint32_t kgd_enable_debug_trap(struct kgd_dev *kgd,
data = 0;
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);

data = 0;
data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
VMID_SEL, 1<<vmid);
data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
TRAP_EN, 1);
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);

WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), orig_stall_vmid);

mutex_unlock(&adev->grbm_idx_mutex);
@@ -890,8 +883,6 @@ static uint32_t kgd_disable_debug_trap(struct kgd_dev *kgd)

mutex_lock(&adev->grbm_idx_mutex);

WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), 0);

WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);

11 changes: 11 additions & 0 deletions drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
Original file line number Diff line number Diff line change
@@ -2003,6 +2003,8 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
int i;
uint32_t sh_mem_config;
uint32_t sh_mem_bases;
uint32_t trap_config_vmid_mask = 0;
uint32_t data;

/*
* Configure apertures:
@@ -2022,6 +2024,9 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
/* CP and shaders */
WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);

/* Calculate trap config vmid mask */
trap_config_vmid_mask |= (1 << i);
}
soc15_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex);
@@ -2034,6 +2039,12 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
}
data = 0;
data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
VMID_SEL, trap_config_vmid_mask);
data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
TRAP_EN, 1);
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
}

static void gfx_v9_0_constants_init(struct amdgpu_device *adev)

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