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ARM: imx6ul: add fec bits to GPR syscon definition
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FEC requires additional bits to select refrence clock.

Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Fugang Duan authored and Shawn Guo committed Aug 5, 2015
1 parent cec13c2 commit 9f55eb9
Showing 1 changed file with 8 additions and 0 deletions.
8 changes: 8 additions & 0 deletions include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -435,4 +435,12 @@
#define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1)
#define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1)

/* For imx6ul iomux gpr register field define */
#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17)
#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18)
#define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17)
#define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18)
#define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17)
#define IMX6UL_GPR1_ENET_CLK_OUTPUT (0x3 << 17)

#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */

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