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drm/i915/dsc: stop using interim structure for calculated params
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Stop using an interim structure rc_parameters for storing calculated
params and then setting drm_dsc_config using that structure. Instead put
calculated params into the struct drm_dsc_config directly.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230517102807.2181589-5-dmitry.baryshkov@linaro.org
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Dmitry Baryshkov authored and Rodrigo Vivi committed May 19, 2023
1 parent 2b470e5 commit 9ff6b52
Showing 1 changed file with 26 additions and 74 deletions.
100 changes: 26 additions & 74 deletions drivers/gpu/drm/i915/display/intel_vdsc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -19,17 +19,6 @@
#include "intel_vdsc.h"
#include "intel_vdsc_regs.h"

struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
u16 initial_offset;
u8 flatness_min_qp;
u8 flatness_max_qp;
u8 rc_quant_incr_limit0;
u8 rc_quant_incr_limit1;
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};

bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
Expand Down Expand Up @@ -64,8 +53,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
}

static void
calculate_rc_params(struct rc_parameters *rc,
struct drm_dsc_config *vdsc_cfg)
calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
int bpc = vdsc_cfg->bits_per_component;
int bpp = vdsc_cfg->bits_per_pixel >> 4;
Expand All @@ -85,56 +73,57 @@ calculate_rc_params(struct rc_parameters *rc,
u32 res, buf_i, bpp_i;

if (vdsc_cfg->slice_height >= 8)
rc->first_line_bpg_offset =
vdsc_cfg->first_line_bpg_offset =
12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
else
rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);

/* Our hw supports only 444 modes as of today */
if (bpp >= 12)
rc->initial_offset = 2048;
vdsc_cfg->initial_offset = 2048;
else if (bpp >= 10)
rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
else if (bpp >= 8)
rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
else
rc->initial_offset = 6144;
vdsc_cfg->initial_offset = 6144;

/* initial_xmit_delay = rc_model_size/2/compression_bpp */
rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);

rc->flatness_min_qp = 3 + qp_bpc_modifier;
rc->flatness_max_qp = 12 + qp_bpc_modifier;
vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;

rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;

bpp_i = (2 * (bpp - 6));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
u8 range_bpg_offset;

/* Read range_minqp and range_max_qp from qp tables */
rc->rc_range_params[buf_i].range_min_qp =
vdsc_cfg->rc_range_params[buf_i].range_min_qp =
intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
rc->rc_range_params[buf_i].range_max_qp =
vdsc_cfg->rc_range_params[buf_i].range_max_qp =
intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);

/* Calculate range_bgp_offset */
/* Calculate range_bpg_offset */
if (bpp <= 6) {
rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
range_bpg_offset = ofs_und6[buf_i];
} else if (bpp <= 8) {
res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
rc->rc_range_params[buf_i].range_bpg_offset =
ofs_und6[buf_i] + res;
range_bpg_offset = ofs_und6[buf_i] + res;
} else if (bpp <= 12) {
rc->rc_range_params[buf_i].range_bpg_offset =
ofs_und8[buf_i];
range_bpg_offset = ofs_und8[buf_i];
} else if (bpp <= 15) {
res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
rc->rc_range_params[buf_i].range_bpg_offset =
ofs_und12[buf_i] + res;
range_bpg_offset = ofs_und12[buf_i] + res;
} else {
rc->rc_range_params[buf_i].range_bpg_offset =
ofs_und15[buf_i];
range_bpg_offset = ofs_und15[buf_i];
}

vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
}
}

Expand Down Expand Up @@ -167,10 +156,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
int err;
u8 i = 0;
int ret;

vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
Expand Down Expand Up @@ -238,43 +224,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
* parameters
*/
if (DISPLAY_VER(dev_priv) >= 13) {
rc = kmalloc(sizeof(*rc), GFP_KERNEL);
if (!rc)
return -ENOMEM;

calculate_rc_params(rc, vdsc_cfg);
rc_params = rc;
calculate_rc_params(vdsc_cfg);
} else {
ret = drm_dsc_setup_rc_params(vdsc_cfg);
if (ret)
return ret;

goto out;
}

vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
vdsc_cfg->initial_offset = rc_params->initial_offset;
vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;

for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
vdsc_cfg->rc_range_params[i].range_min_qp =
rc_params->rc_range_params[i].range_min_qp;
vdsc_cfg->rc_range_params[i].range_max_qp =
rc_params->rc_range_params[i].range_max_qp;
/*
* Range BPG Offset uses 2's complement and is only a 6 bits. So
* mask it to get only 6 bits.
*/
vdsc_cfg->rc_range_params[i].range_bpg_offset =
rc_params->rc_range_params[i].range_bpg_offset &
DSC_RANGE_BPG_OFFSET_MASK;
}

if (DISPLAY_VER(dev_priv) < 13) {
/*
* FIXME: verify that the hardware actually needs these
* modifications rather than them being simple typos.
Expand All @@ -288,7 +243,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}

out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
Expand All @@ -303,8 +257,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);

kfree(rc);

return 0;
}

Expand Down

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