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arm64: dts: qcom: sm8650: Use GIC-ITS for PCIe0 and PCIe1
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Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs
received from endpoint devices to the CPU using GIC-ITS MSI controller.
Add support for it.

The GIC-ITS MSI implementation provides an advantage over internal MSI
implementation using Locality-specific Peripheral Interrupts (LPI) that
would allow MSIs to be targeted for each CPU core.

Like SM8450 & SM8550, the IDs are swapped, but works fine on PCIe0 and PCIe1.

WiFi PCIe Device on SM8650-QRD using GIC-ITS:
159:          0          0          0          0          0          0          0          0   ITS-MSI   0 Edge      PCIe PME, aerdrv
167:          0          4          0          0          0          0          0          0   ITS-MSI 524288 Edge      bhi
168:          0          0          4          0          0          0          0          0   ITS-MSI 524289 Edge      mhi
169:          0          0          0         34          0          0          0          0   ITS-MSI 524290 Edge      mhi
170:          0          0          0          0          3          0          0          0   ITS-MSI 524291 Edge      ce0
171:          0          0          0          0          0          2          0          0   ITS-MSI 524292 Edge      ce1
172:          0          0          0          0          0          0        806          0   ITS-MSI 524293 Edge      ce2
173:          0          0          0          0          0          0          0         76   ITS-MSI 524294 Edge      ce3
174:          0          0          0          0          0          0          0          0   ITS-MSI 524295 Edge      ce5
175:          0         13          0          0          0          0          0          0   ITS-MSI 524296 Edge      DP_EXT_IRQ
176:          0          0          0          0          0          0          0          0   ITS-MSI 524297 Edge      DP_EXT_IRQ
177:          0          0          0       5493          0          0          0          0   ITS-MSI 524298 Edge      DP_EXT_IRQ
178:          0          0          0          0         82          0          0          0   ITS-MSI 524299 Edge      DP_EXT_IRQ
179:          0          0          0          0          0       7204          0          0   ITS-MSI 524300 Edge      DP_EXT_IRQ
180:          0          0          0          0          0          0        672          0   ITS-MSI 524301 Edge      DP_EXT_IRQ
181:          0          0          0          0          0          0          0         30   ITS-MSI 524302 Edge      DP_EXT_IRQ

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240125-topic-sm8650-upstream-pcie-its-v1-1-cb506deeb43e@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Neil Armstrong authored and Bjorn Andersson committed Feb 3, 2024
1 parent 8385383 commit a33a532
Showing 1 changed file with 8 additions and 0 deletions.
8 changes: 8 additions & 0 deletions arch/arm64/boot/dts/qcom/sm8650.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -2269,6 +2269,10 @@
interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>;

/* Entries are reversed due to the unusual ITS DeviceID encoding */
msi-map = <0x0 &gic_its 0x1401 0x1>,
<0x100 &gic_its 0x1400 0x1>;

linux,pci-domain = <0>;
num-lanes = <2>;
bus-range = <0 0xff>;
Expand Down Expand Up @@ -2392,6 +2396,10 @@
interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>;

/* Entries are reversed due to the unusual ITS DeviceID encoding */
msi-map = <0x0 &gic_its 0x1481 0x1>,
<0x100 &gic_its 0x1480 0x1>;

linux,pci-domain = <1>;
num-lanes = <2>;
bus-range = <0 0xff>;
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