-
Notifications
You must be signed in to change notification settings - Fork 0
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Merge branch 'net-ethernet-ti-add-networking-support-for-k3-am65x-j72…
…1e-soc' Grygorii Strashko says: ==================== net: ethernet: ti: add networking support for k3 am65x/j721e soc This v6 series adds basic networking support support TI K3 AM654x/J721E SoC which have integrated Gigabit Ethernet MAC (Media Access Controller) into device MCU domain and named MCU_CPSW0 (CPSW2G NUSS). Formally TRMs refer CPSW2G NUSS as two-port Gigabit Ethernet Switch subsystem with port 0 being the CPPI DMA host port and port 1 being the external Ethernet port, but for 1 external port device it's just Port 0 <-> ALE <-> Port 1 and it's rather device with HW filtering capabilities then actually switching device. It's expected to have similar devices, but with more external ports. The new Host port 0 Communications Port Programming Interface (CPPI5) is operating by TI AM654x/J721E NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller [1]. The CPSW2G contains below modules for which existing code is re-used: - MAC SL: cpsw_sl.c - Address Lookup Engine (ALE): cpsw_ale.c, basically compatible with K2 66AK2E/G - Management Data Input/Output interface (MDIO): davinci_mdio.c, fully compatible with TI AM3/4/5 devices Basic features supported by CPSW2G NUSS driver: - VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on ingress, Auto VLAN removal on egress and auto pad to minimum frame size. - multicast filtering - promisc mode - TX multiq support in Round Robin or Fixed priority modes - RX checksum offload for non-fragmented IPv4/IPv6 TCP/UDP packets - TX checksum offload support for IPv4/IPv6 TCP/UDP packets (J721E only). Features under development: - Support for IEEE 1588 Clock Synchronization. The CPSW2G NUSS includes new version of Common Platform Time Sync (CPTS) - tc-mqprio: priority level Quality Of Service (QOS) support (802.1p) - tc-cbs: Support for Audio/Video Bridging (P802.1Qav/D6.0) HW shapers - tc-taprio: IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic - frame preemption: IEEE P902.3br/D2.0 Interspersing Express Traffic, 802.1Qbu - extended ALE features: classifier/policers, auto-aging Patches 1-6 are intended for netdev, Patches 7-11 are intended for K3 Platform tree and provided here for testing purposes. Changes in v6: - fixed comments from Rob Herring <robh@kernel.org> and added his Reviewed-by. - added Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Changes in v5: - renamed files k3-udma-desc-pool.* k3-udma-desc-pool to k3-cppi-desc-pool.*, and API to k3_cppi_desc_pool_* as requested by Peter Ujfalusi <peter.ujfalusi@ti.com> - fixed copy-paste err in am65_cpsw_nuss_ndo_slave_set_rx_mode() which blocked recieving of mcast frames. - added Tested-by: Murali Karicheri <m-karicheri2@ti.com> Changes in v4: - fixed minor comments from Jakub Kicinski <kuba@kernel.org> - dependencies resolved: required phy-rmii-sel changes [2] queued for merge except one [3] which is included in this series with Kishon's ask. Changes in v3: - add ARM64 defconfig changes for testing purposes - fixed DT yaml definition - fixed comments from Jakub Kicinski <kuba@kernel.org> Changes in v2: - fixed DT yaml definition - fixed comments from David Miller v5: https://patchwork.ozlabs.org/cover/1258295/ v4: https://patchwork.ozlabs.org/cover/1256092/ v3: https://patchwork.ozlabs.org/cover/1254568/ v2: https://patchwork.ozlabs.org/cover/1250674/ v1: https://lwn.net/Articles/813087/ TRMs: AM654: http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf J721E: http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf Preliminary documentation can be found at: http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/K3_CPSW2g.html [1] https://lwn.net/Articles/808030/ [2] https://lkml.org/lkml/2020/2/22/100 [3] https://lkml.org/lkml/2020/3/3/724 ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
- Loading branch information
Showing
18 changed files
with
3,486 additions
and
5 deletions.
There are no files selected for viewing
225 changes: 225 additions & 0 deletions
225
Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,225 @@ | ||
| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
|
||
| title: The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings | ||
|
|
||
| maintainers: | ||
| - Grygorii Strashko <grygorii.strashko@ti.com> | ||
| - Sekhar Nori <nsekhar@ti.com> | ||
|
|
||
| description: | ||
| The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports | ||
| (one external) and provides Ethernet packet communication for the device. | ||
| CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII), | ||
| Reduced Media Independent Interface (RMII), the Management Data | ||
| Input/Output (MDIO) interface for physical layer device (PHY) management, | ||
| new version of Common Platform Time Sync (CPTS), updated Address Lookup | ||
| Engine (ALE). | ||
| One external Ethernet port (port 1) with selectable RGMII/RMII interfaces and | ||
| an internal Communications Port Programming Interface (CPPI5) (Host port 0). | ||
| Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels | ||
| and one RX channels and operating by TI AM654x/J721E NAVSS Unified DMA | ||
| Peripheral Root Complex (UDMA-P) controller. | ||
| The CPSW2G NUSS is integrated into device MCU domain named MCU_CPSW0. | ||
|
|
||
| Additional features | ||
| priority level Quality Of Service (QOS) support (802.1p) | ||
| Support for Audio/Video Bridging (P802.1Qav/D6.0) | ||
| Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F) | ||
| Flow Control (802.3x) Support | ||
| Time Sensitive Network Support | ||
| IEEE P902.3br/D2.0 Interspersing Express Traffic | ||
| IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic | ||
| Configurable number of addresses plus VLANs | ||
| Configurable number of classifier/policers | ||
| VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on | ||
| ingress, Auto VLAN removal on egress and auto pad to minimum frame size. | ||
| RX/TX csum offload | ||
|
|
||
| Specifications can be found at | ||
| http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf | ||
| http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf | ||
|
|
||
| properties: | ||
| "#address-cells": true | ||
| "#size-cells": true | ||
|
|
||
| compatible: | ||
| oneOf: | ||
| - const: ti,am654-cpsw-nuss | ||
| - const: ti,j721e-cpsw-nuss | ||
|
|
||
| reg: | ||
| maxItems: 1 | ||
| description: | ||
| The physical base address and size of full the CPSW2G NUSS IO range | ||
|
|
||
| reg-names: | ||
| items: | ||
| - const: cpsw_nuss | ||
|
|
||
| ranges: true | ||
|
|
||
| dma-coherent: true | ||
|
|
||
| clocks: | ||
| description: CPSW2G NUSS functional clock | ||
|
|
||
| clock-names: | ||
| items: | ||
| - const: fck | ||
|
|
||
| power-domains: | ||
| maxItems: 1 | ||
|
|
||
| dmas: | ||
| maxItems: 9 | ||
|
|
||
| dma-names: | ||
| items: | ||
| - const: tx0 | ||
| - const: tx1 | ||
| - const: tx2 | ||
| - const: tx3 | ||
| - const: tx4 | ||
| - const: tx5 | ||
| - const: tx6 | ||
| - const: tx7 | ||
| - const: rx | ||
|
|
||
| ethernet-ports: | ||
| type: object | ||
| properties: | ||
| '#address-cells': | ||
| const: 1 | ||
| '#size-cells': | ||
| const: 0 | ||
|
|
||
| patternProperties: | ||
| port@1: | ||
| type: object | ||
| description: CPSW2G NUSS external ports | ||
|
|
||
| allOf: | ||
| - $ref: ethernet-controller.yaml# | ||
|
|
||
| properties: | ||
| reg: | ||
| items: | ||
| - const: 1 | ||
| description: CPSW port number | ||
|
|
||
| phys: | ||
| maxItems: 1 | ||
| description: phandle on phy-gmii-sel PHY | ||
|
|
||
| label: | ||
| description: label associated with this port | ||
|
|
||
| ti,mac-only: | ||
| $ref: /schemas/types.yaml#definitions/flag | ||
| description: | ||
| Specifies the port works in mac-only mode. | ||
|
|
||
| ti,syscon-efuse: | ||
| $ref: /schemas/types.yaml#definitions/phandle-array | ||
| description: | ||
| Phandle to the system control device node which provides access | ||
| to efuse IO range with MAC addresses | ||
|
|
||
| required: | ||
| - reg | ||
| - phys | ||
|
|
||
| additionalProperties: false | ||
|
|
||
| patternProperties: | ||
| "^mdio@[0-9a-f]+$": | ||
| type: object | ||
| allOf: | ||
| - $ref: "ti,davinci-mdio.yaml#" | ||
| description: | ||
| CPSW MDIO bus. | ||
|
|
||
| required: | ||
| - compatible | ||
| - reg | ||
| - reg-names | ||
| - ranges | ||
| - clocks | ||
| - clock-names | ||
| - power-domains | ||
| - dmas | ||
| - dma-names | ||
| - '#address-cells' | ||
| - '#size-cells' | ||
|
|
||
| additionalProperties: false | ||
|
|
||
| examples: | ||
| - | | ||
| #include <dt-bindings/pinctrl/k3.h> | ||
| #include <dt-bindings/soc/ti,sci_pm_domain.h> | ||
| #include <dt-bindings/net/ti-dp83867.h> | ||
| mcu_cpsw: ethernet@46000000 { | ||
| compatible = "ti,am654-cpsw-nuss"; | ||
| #address-cells = <2>; | ||
| #size-cells = <2>; | ||
| reg = <0x0 0x46000000 0x0 0x200000>; | ||
| reg-names = "cpsw_nuss"; | ||
| ranges = <0x0 0x0 0x46000000 0x0 0x200000>; | ||
| dma-coherent; | ||
| clocks = <&k3_clks 5 10>; | ||
| clock-names = "fck"; | ||
| power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; | ||
| dmas = <&mcu_udmap 0xf000>, | ||
| <&mcu_udmap 0xf001>, | ||
| <&mcu_udmap 0xf002>, | ||
| <&mcu_udmap 0xf003>, | ||
| <&mcu_udmap 0xf004>, | ||
| <&mcu_udmap 0xf005>, | ||
| <&mcu_udmap 0xf006>, | ||
| <&mcu_udmap 0xf007>, | ||
| <&mcu_udmap 0x7000>; | ||
| dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", | ||
| "rx"; | ||
| ethernet-ports { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| cpsw_port1: port@1 { | ||
| reg = <1>; | ||
| ti,mac-only; | ||
| label = "port1"; | ||
| ti,syscon-efuse = <&mcu_conf 0x200>; | ||
| phys = <&phy_gmii_sel 1>; | ||
| phy-mode = "rgmii-rxid"; | ||
| phy-handle = <&phy0>; | ||
| }; | ||
| }; | ||
| davinci_mdio: mdio@f00 { | ||
| compatible = "ti,cpsw-mdio","ti,davinci_mdio"; | ||
| reg = <0x0 0xf00 0x0 0x100>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| clocks = <&k3_clks 5 10>; | ||
| clock-names = "fck"; | ||
| bus_freq = <1000000>; | ||
| phy0: ethernet-phy@0 { | ||
| reg = <0>; | ||
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; | ||
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; | ||
| }; | ||
| }; | ||
| }; |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -30,6 +30,7 @@ | |
| i2c3 = &main_i2c1; | ||
| i2c4 = &main_i2c2; | ||
| i2c5 = &main_i2c3; | ||
| ethernet0 = &cpsw_port1; | ||
| }; | ||
|
|
||
| chosen { }; | ||
|
|
||
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Oops, something went wrong.