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Merge tag 'phy-for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/…
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…git/kishon/linux-phy into usb-testing

Kishon writes:

phy: for 4.6

*) Add driver for rockchip Display Port PHY
*) Add driver for the Rockchip SoC internal eMMC PHY
*) Add usb-uart functionality in rockchip-usb
*) cleanup rcar usb2 PHY driver
*) Fix for randconfig error

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Greg Kroah-Hartman committed Mar 5, 2016
2 parents 69bec72 + 89636ad commit a567500
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15 changes: 4 additions & 11 deletions Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
Original file line number Diff line number Diff line change
Expand Up @@ -7,33 +7,26 @@ Required properties:
- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
SoC.
- reg: offset and length of the partial USB 2.0 Host register block.
- reg-names: must be "usb2_host".
- clocks: clock phandle and specifier pair(s).
- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.

Optional properties:
To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are
combined, the device tree node should set HSUSB properties to reg and reg-names
properties. This is because HSUSB has registers to select USB 2.0 host or
peripheral at that channel:
- reg: offset and length of the partial HSUSB register block.
- reg-names: must be "hsusb".
combined, the device tree node should set interrupt properties to use the
channel as USB OTG:
- interrupts: interrupt specifier for the PHY.

Example (R-Car H3):

usb-phy@ee080200 {
compatible = "renesas,usb2-phy-r8a7795";
reg = <0 0xee080200 0 0x700>, <0 0xe6590100 0 0x100>;
reg-names = "usb2_host", "hsusb";
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7795_CLK_EHCI0>,
<&mstp7_clks R8A7795_CLK_HSUSB>;
clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
};

usb-phy@ee0a0200 {
compatible = "renesas,usb2-phy-r8a7795";
reg = <0 0xee0a0200 0 0x700>;
reg-names = "usb2_host";
clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
};
22 changes: 22 additions & 0 deletions Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
Rockchip specific extensions to the Analogix Display Port PHY
------------------------------------

Required properties:
- compatible : should be one of the following supported values:
- "rockchip.rk3288-dp-phy"
- clocks: from common clock binding: handle to dp clock.
of memory mapped region.
- clock-names: from common clock binding:
Required elements: "24m"
- rockchip,grf: phandle to the syscon managing the "general register files"
- #phy-cells : from the generic PHY bindings, must be 0;

Example:

edp_phy: edp-phy {
compatible = "rockchip,rk3288-dp-phy";
rockchip,grf = <&grf>;
clocks = <&cru SCLK_EDP_24M>;
clock-names = "24m";
#phy-cells = <0>;
};
19 changes: 19 additions & 0 deletions Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,19 @@
Rockchip EMMC PHY
-----------------------

Required properties:
- compatible: rockchip,rk3399-emmc-phy
- rockchip,grf : phandle to the syscon managing the "general
register files"
- #phy-cells: must be 0
- reg: PHY configure reg address offset in "general
register files"

Example:

emmcphy: phy {
compatible = "rockchip,rk3399-emmc-phy";
rockchip,grf = <&grf>;
reg = <0xf780>;
#phy-cells = <0>;
};
6 changes: 6 additions & 0 deletions Documentation/kernel-parameters.txt
Original file line number Diff line number Diff line change
Expand Up @@ -3491,6 +3491,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.

ro [KNL] Mount root device read-only on boot

rockchip.usb_uart
Enable the uart passthrough on the designated usb port
on Rockchip SoCs. When active, the signals of the
debug-uart get routed to the D+ and D- pins of the usb
port and the regular usb controller gets disabled.

root= [KNL] Root filesystem
See name_to_dev_t comment in init/do_mounts.c.

Expand Down
16 changes: 15 additions & 1 deletion drivers/phy/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ config PHY_BERLIN_SATA
config ARMADA375_USBCLUSTER_PHY
def_bool y
depends on MACH_ARMADA_375 || COMPILE_TEST
depends on OF
depends on OF && HAS_IOMEM
select GENERIC_PHY

config PHY_DM816X_USB
Expand Down Expand Up @@ -337,6 +337,20 @@ config PHY_ROCKCHIP_USB
help
Enable this to support the Rockchip USB 2.0 PHY.

config PHY_ROCKCHIP_EMMC
tristate "Rockchip EMMC PHY Driver"
depends on ARCH_ROCKCHIP && OF
select GENERIC_PHY
help
Enable this to support the Rockchip EMMC PHY.

config PHY_ROCKCHIP_DP
tristate "Rockchip Display Port PHY Driver"
depends on ARCH_ROCKCHIP && OF
select GENERIC_PHY
help
Enable this to support the Rockchip Display Port PHY.

config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
Expand Down
2 changes: 2 additions & 0 deletions drivers/phy/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,8 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
Expand Down
83 changes: 11 additions & 72 deletions drivers/phy/phy-rcar-gen3-usb2.c
Original file line number Diff line number Diff line change
Expand Up @@ -74,29 +74,15 @@
#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
#define USB2_ADPCTRL_DRVVBUS BIT(4)

/******* HSUSB registers (original offset is +0x100) *******/
#define HSUSB_LPSTS 0x02
#define HSUSB_UGCTRL2 0x84

/* Low Power Status register (LPSTS) */
#define HSUSB_LPSTS_SUSPM 0x4000

/* USB General control register 2 (UGCTRL2) */
#define HSUSB_UGCTRL2_MASK 0x00000031 /* bit[31:6] should be 0 */
#define HSUSB_UGCTRL2_USB0SEL 0x00000030
#define HSUSB_UGCTRL2_USB0SEL_HOST 0x00000010
#define HSUSB_UGCTRL2_USB0SEL_HS_USB 0x00000020
#define HSUSB_UGCTRL2_USB0SEL_OTG 0x00000030

struct rcar_gen3_data {
void __iomem *base;
struct clk *clk;
};

struct rcar_gen3_chan {
struct rcar_gen3_data usb2;
struct rcar_gen3_data hsusb;
struct phy *phy;
bool has_otg;
};

static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
Expand Down Expand Up @@ -202,24 +188,15 @@ static int rcar_gen3_phy_usb2_init(struct phy *p)
{
struct rcar_gen3_chan *channel = phy_get_drvdata(p);
void __iomem *usb2_base = channel->usb2.base;
void __iomem *hsusb_base = channel->hsusb.base;
u32 val;

/* Initialize USB2 part */
writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);

/* Initialize HSUSB part */
if (hsusb_base) {
val = readl(hsusb_base + HSUSB_UGCTRL2);
val = (val & ~HSUSB_UGCTRL2_USB0SEL) |
HSUSB_UGCTRL2_USB0SEL_OTG;
writel(val & HSUSB_UGCTRL2_MASK, hsusb_base + HSUSB_UGCTRL2);

/* Initialize otg part */
/* Initialize otg part */
if (channel->has_otg)
rcar_gen3_init_otg(channel);
}

return 0;
}
Expand All @@ -237,7 +214,6 @@ static int rcar_gen3_phy_usb2_power_on(struct phy *p)
{
struct rcar_gen3_chan *channel = phy_get_drvdata(p);
void __iomem *usb2_base = channel->usb2.base;
void __iomem *hsusb_base = channel->hsusb.base;
u32 val;

val = readl(usb2_base + USB2_USBCTR);
Expand All @@ -246,41 +222,13 @@ static int rcar_gen3_phy_usb2_power_on(struct phy *p)
val &= ~USB2_USBCTR_PLL_RST;
writel(val, usb2_base + USB2_USBCTR);

/*
* TODO: To reduce power consuming, this driver should set the SUSPM
* after the PHY detects ID pin as peripheral.
*/
if (hsusb_base) {
/* Power on HSUSB PHY */
val = readw(hsusb_base + HSUSB_LPSTS);
val |= HSUSB_LPSTS_SUSPM;
writew(val, hsusb_base + HSUSB_LPSTS);
}

return 0;
}

static int rcar_gen3_phy_usb2_power_off(struct phy *p)
{
struct rcar_gen3_chan *channel = phy_get_drvdata(p);
void __iomem *hsusb_base = channel->hsusb.base;
u32 val;

if (hsusb_base) {
/* Power off HSUSB PHY */
val = readw(hsusb_base + HSUSB_LPSTS);
val &= ~HSUSB_LPSTS_SUSPM;
writew(val, hsusb_base + HSUSB_LPSTS);
}

return 0;
}

static struct phy_ops rcar_gen3_phy_usb2_ops = {
.init = rcar_gen3_phy_usb2_init,
.exit = rcar_gen3_phy_usb2_exit,
.power_on = rcar_gen3_phy_usb2_power_on,
.power_off = rcar_gen3_phy_usb2_power_off,
.owner = THIS_MODULE,
};

Expand Down Expand Up @@ -313,6 +261,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
struct rcar_gen3_chan *channel;
struct phy_provider *provider;
struct resource *res;
int irq;

if (!dev->of_node) {
dev_err(dev, "This driver needs device tree\n");
Expand All @@ -323,29 +272,19 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
if (!channel)
return -ENOMEM;

res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usb2_host");
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
channel->usb2.base = devm_ioremap_resource(dev, res);
if (IS_ERR(channel->usb2.base))
return PTR_ERR(channel->usb2.base);

/* "hsusb" memory resource is optional */
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsusb");

/* To avoid error message by devm_ioremap_resource() */
if (res) {
int irq;

channel->hsusb.base = devm_ioremap_resource(dev, res);
if (IS_ERR(channel->hsusb.base))
channel->hsusb.base = NULL;
/* call request_irq for OTG */
irq = platform_get_irq(pdev, 0);
if (irq >= 0)
irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
IRQF_SHARED, dev_name(dev),
channel);
/* call request_irq for OTG */
irq = platform_get_irq(pdev, 0);
if (irq >= 0) {
irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
IRQF_SHARED, dev_name(dev), channel);
if (irq < 0)
dev_err(dev, "No irq handler (%d)\n", irq);
channel->has_otg = true;
}

/* devm_phy_create() will call pm_runtime_enable(dev); */
Expand Down
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